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TAB A
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Halepete I. U.S. Patent No. 7,100,061 ..................................................................................................................................................1 Belgard II. U.S. Patent No. 5,895,503...............................................................................................................................................11 III. U.S. Patent No. 6,226,733..............................................................................................................................................24 IV. U.S. Patent No. 6,430,668 .............................................................................................................................................90 V. U.S. Patent No. 6,813,699.............................................................................................................................................112 Garg (Multiple-Type Registers) VI. U.S. Patent No. 5,493,687 ...........................................................................................................................................129 VII. U.S. Patent No. 5,838,986 ..........................................................................................................................................134 VIII. U.S. Patent No. 6,044,449.........................................................................................................................................141 Garg (Register Renaming) IX. U.S. Patent No. 5,737,624 ...........................................................................................................................................144 X. U.S. Patent No. 5,974,526.............................................................................................................................................154 XI. U.S. Patent No. 6,289,433 ...........................................................................................................................................165
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JOINT CHART TAB A TRANSMETA PATENTS I. THE `061 PATENT (HALEPETE)*
`061 Patent
Claim Language 1. A method for controlling power consumption of a computer processor on a chip comprising the steps of: determining a maximum allowable power consumption level from an operating condition of the processor, said computer processor determining a maximum frequency which provides power not greater than the allowable power consumption level, said computer processor determining a minimum voltage which allows operation at the maximum frequency determined, and Transmeta Proposed Constructions Intel Proposed Constructions
"determining a maximum allowable power consumption level from an operating condition of the processor, said computer processor determining a maximum frequency which provides power not greater than the allowable power consumption level, said computer processor determining a minimum voltage which allows operation at the maximum frequency determined" means that based on an operating condition of the processor, the computer processor determines a maximum allowable power consumption level by determining a corresponding maximum frequency and a minimum voltage which allows operation at the maximum frequency. [Term 1] Intrinsic Evidence: see, e.g., `061, claims 9, 10, 12, 15, 39; `061, Fig. 2, 1:4256, 3:20-26, 3:47-4:8, 5:21-6:40, 7:40-53; Prosecution History: `061, Paper 20, pp. 24-27; Paper 26, pp. 14-16, 20-21; 8/27/07 Reexam Reply, p. 14.
"determining a maximum allowable power consumption level from an operating condition of the processor, said computer processor determining a maximum frequency which provides power not greater than the allowable power consumption level, said computer processor determining a minimum voltage which allows operation at the maximum frequency determined" means after determining a maximum allowable power consumption level from an operating condition of the processor, the computer processor determines, in a separate step, a maximum frequency which provides power not greater than the determined allowable power consumption level, and the computer processor determines, in another separate step, a minimum voltage which allows operation at the determined maximum frequency. [Term 1] Intrinsic Evidence: `061 patent at Fig. 2; 1:48-50; 3:20-26; 3:47-4:8; 5:21-57; 5:63-
* `061 patent asserted claims 2-7, 16-22, 24-29, 32-38, 40-51, 52-54 and 57 are not included in this chart, because there are no disputed terms for those asserted claims.
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`061 Patent
Claim Language Transmeta Proposed Constructions Intel Proposed Constructions 67; 6:1-40; 7:40-53; claims 2-3; claim 10; claim 15; `061 File History at Amendment and Response dated February 19, 2004, pp. 2-7, 9, 15-17, 23; Reply to Office Action in Inter Partes Reexamination dated August 27, 2007, pp. 20-23, 28-32, 34-35, 40, 42-43, 48-50, 52-53. "determining a . . . frequency. . . [and a] voltage" means determine a frequency and a voltage based at least on analyzing commands to be executed by the processor. [Term 2] Intrinsic Evidence: '061 patent at Abstract; Fig. 2; 2:22-24; 5:21-57; 6:1-40; 7:40-53; claims 2-3; claims 17-22.
"determining a . . . frequency. . . [and a] voltage" No construction necessary plain and ordinary meaning. [Term 2] Intrinsic Evidence: `061, 5:43-45, 63-67; Prosecution History: `061, Paper 17, pp. 19-22, Paper 26, pp. 14-17, 22-23.
dynamically changing the power consumption of the processor by changing frequency and voltage, respectively, to the maximum frequency and the minimum voltage determined, wherein said dynamically changing the power consumption comprises executing instructions in said computer processor while changing voltage at which said computer processor is operated. 8. A computing device comprising: a power supply furnishing selectable output voltages, a clock frequency source,
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`061 Patent
Claim Language a central processor including: a processing unit for providing values indicative of operating conditions of the central processor, and a clock frequency generator receiving a clock frequency from the clock frequency source and providing one of a plurality of selectable output clock frequencies to the processing unit; Transmeta Proposed Constructions Intel Proposed Constructions
"clock frequency generator" means a unit that provides individual clock frequencies for each of a plurality of components including a processing unit of the processor, the system memory, and the system bus. [Term 3.] Intrinsic Evidence: `061 patent at Fig. 1; Fig. 2; Fig. 3; 1:56-2:7; 3:18-46; 3:604:45; 5:54-63; `061 File History at Amendment and Response dated September 27, 2001, pp. 4-6. "means for detecting the values means for detecting the values indicative "means for detecting the values of operating conditions of the central indicative of operating conditions of the indicative of operating conditions of the processor and causing the power supply central processor and causing the power central processor and causing the power and clock frequency generator to supply and clock frequency generator to supply and clock frequency generator to furnish an output clock frequency and furnish an output clock frequency and furnish an output clock frequency and voltage level for the central processor voltage level for the central processor voltage level for the central processor and to generate concurrently and to generate concurrently and to generate concurrently frequencies which are selected for frequencies which are selected for frequencies which are selected for optimum operation of a plurality of optimum operation of a plurality of optimum operation of a plurality of functional units of the computing device; functional units of the computing functional units of the computing and device" This is a means-plus-function device" This is a means-plus-function limitation that must be construed according limitation that must be construed according to 35 U.S.C. §112, ¶ 6. [Term 4] to 35 U.S.C. §112, ¶ 6. [Term 4] Function: The function performed by the claimed Function: detecting the values indicative of operating
"clock frequency generator" No construction necessary plain and ordinary meaning. [Term 3] Intrinsic Evidence: `061, Fig. 1, element 17; 3:18-26; Prosecution History: `061, Paper 5, pp. 4-8, Paper 9, pp. 6-9, Paper 14, pp. 3-6; Paper 26, pp. 22, 24..
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`061 Patent
Claim Language Transmeta Proposed Constructions "means for detecting . . . and causing" is detecting the values indicative of operating conditions of the central processor and causing the power supply and clock frequency generator to furnish an output clock frequency and voltage level for the central processor and to generate concurrently frequencies which are selected for optimum operation of a plurality of functional units of the computing device. Structure: The disclosed structure that corresponds to the function of the claimed "means for detecting . . . and causing" is control software and a set of registers in the processor such as the clock divider register 22 in which are stored a multiplier and dividers computed by the processor (or determined via table lookup) based on operating conditions of the processor. Intrinsic Evidence: see, e.g., `061, claim 9; `061, Fig. 1, master control unit 18; `061, Fig. 3, clock divider register 22, master control register 20, master status register 21; `061, 2:64-3:5, 4:29-54, 5:2167, 7:26-38; Prosecution History: `061, Paper 7, p. 9, Paper 14, pp. 3-6, Paper 20, pp. 24-27; Paper 26, pp. 14-16, 22. Intel Proposed Constructions conditions of the central processor and causing the power supply and clock frequency generator to furnish an output clock frequency and voltage level for the central processor and to generate concurrently frequencies which are selected for optimum operation of a plurality of functional units of the computing device. Structure: control software executing on the processor and the cooperating hardware on the processor Intrinsic Evidence: `061 patent at Fig. 1; Fig. 2; 2:46-3:17; 3:18-4:8; 4:12-20; 4:2932; 4:35-42; 5:15-28; 5:54-6:2; 6:9-13; 6:30-36; 6:41-45; 6:50-54; 7:26-38; 7:4953; claim 9; `061 File History at Amendment and Response dated May 7, 2002, pp. 9-11; Amendment and Response dated January 28, 2003, pp. 3-5; Amendment and Response dated July 7, 2003, pp. 25-27; Amendment and Response dated February 19, 2004, pp. 1516, 22; Amendment and Response dated August 3, 2004, pp. 2-3, 19-20; Reply to Office Action in Inter Partes Reexamination dated August 27, 2007, pp. 24-25, 35-36, 38, 40-41, 46-47, 50-52.
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`061 Patent
Claim Language Transmeta Proposed Constructions operating conditions of the central processor" [Term 12] See claim 15, Term 5. means for executing instructions in said central processor while changing voltage at which said central processor is operated. 15. A method of controlling a computer processor, comprising: monitoring operating conditions internal to said computer processor; Intel Proposed Constructions operating conditions of the central processor" [Term 12] See claim 15, Term 5.
"operating conditions internal to said computer processor" No construction necessary plain and ordinary meaning. If the Court decides a construction is necessary, this term means a plurality of types of operating conditions that are internal to the computer processor. [Term 5] Intrinsic Evidence: see, e.g., `061, claims 1, 39, 44-48; `061, 5:21-45, 5:54-61; Paper 20, pp. 19-20; `061 File History, Paper 21, pp. 2-3; 8/19/04 Notice of Allowability, pp. 1-3. determining a frequency and a voltage at "determining a frequency and a which to operate said computer processor, voltage" No construction necessary plain based on said internal operating and ordinary meaning. [Term 6] conditions; Intrinsic Evidence: `061, 5:43-45, 63-67; Prosecution History: `061, Paper 17, pp. 19-22, Paper 26, pp. 14-17, 22-23.
"operating conditions internal to said computer processor" means a plurality of types of operating conditions, excluding core utilization, that are internal to the computer processor. [Term 5] Intrinsic Evidence: `061 patent at Fig. 2; 5:15-45; 5:54-61; 7:26-38; claim 1; `061 File History at Amendment and Response dated July 7, 2003, pp. 19-20, 22, 25-28; Reply to Office Action in Inter Partes Reexamination dated August 27, 2007, pp. 24-27, 31, 33-36. "determining a frequency and a voltage" means determine a frequency and a voltage based at least on analyzing commands to be executed by the processor. [Term 6] Intrinsic Evidence: '061 patent at Abstract; Fig. 2; 2:22-24; 5:21-57; 6:1-40; 7:40-53; claims 2-3; claims 17-22.
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`061 Patent
Claim Language and implementing the determined frequency and voltage, wherein said implementing comprises: executing instructions in said computer processor while changing voltage at which said computer processor is operated. 23. A method of controlling a computer processor, comprising: monitoring idle time of said computer processor; said computer processor determining a frequency and a voltage at which to operate said computer processor, based on said idle time; and Transmeta Proposed Constructions . Intel Proposed Constructions
"said computer processor determining a frequency and a voltage" No construction necessary plain and ordinary meaning. [Term 7] Intrinsic Evidence: `061 File History, Paper 30, pp. 2-3; 8/3/04 Amendment, pp. 1-25; 8/19/04 Notice of Allowability, pp. 1-3.
"said computer processor determining a frequency and a voltage" means the computer processor itself, not the operating system, determines a frequency and a voltage. [Term 7] Intrinsic Evidence: `061 patent at Fig. 2; 3:20-26; 3:47-4:8; 5:21-57; 6:1-40; 7:4053; claim 10; claims 24-27; claim 29; claims 34-38; claims 40-43; claim 53; `061 File History at Amendment and Response dated February 19, 2004, pp. 2-7, 9, 15-17, 23; Reply to Office Action in Inter Partes Reexamination dated August 27, 2007, pp. 20-23, 28-32, 34-35, 40, 42-43, 48-50, 5253. "determining a frequency and a voltage" See '061 claim 15, Term 6.
"determining a frequency and a voltage" See '061 claim 15, Term 6. implementing the determined frequency and voltage, wherein said implementing
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`061 Patent
Claim Language comprises executing instructions in said computer processor while changing voltage at which said computer processor is operated. 30. A method of controlling a computer processor, comprising: monitoring a state of said computer processor; Transmeta Proposed Constructions Intel Proposed Constructions
"a state of said computer processor" means a condition of the computer processor such as activeness or idleness. [Term 8] Intrinsic Evidence: see, e.g., `061 claims 31-33, 39, 44-52; `061, 4:63-65, 5:21-45, 6:54-56, 7:26-28; Prosecution History: `061, Paper 20, pp. 19-21. "said computer processor determining a frequency and a voltage" See `061 claim 23, Term 7. "determining a frequency and a voltage" See '061 claim 15, Term 6.
said computer processor determining a frequency and a voltage at which to operate said computer processor, based on said state; and
"a state of said computer processor" means the activeness or idleness of the computer processor. [Term 8] Intrinsic Evidence: `061 patent at Fig. 2; Fig. 4; 4:63-5:14; 5:21-45; 6:54-56; 7:2628; 7:49-53; claims 31-33; claim 39; claims 48-52; Reply to Office Action in Inter Partes Reexamination dated August 27, 2007, pp. 25, 29, 53. "said computer processor determining a frequency and a voltage" See `061 claim 23, Term 7. "determining a frequency and a voltage" See '061 claim 15, Term 6.
implementing the determined frequency and voltage, wherein said implementing comprises executing instructions in said computer processor while changing voltage at which said computer processor is operated. 31. The method of claim 30, wherein said state comprises a sleep state.
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`061 Patent
Claim Language 39. A method of managing power consumption comprising: monitoring internal conditions of a computer processor; Transmeta Proposed Constructions Intel Proposed Constructions
"internal conditions of a computer processor" No construction necessary plain and ordinary meaning. If the Court decides a construction is necessary, this term means a plurality of types of operating conditions that are internal to the computer processor. [Term 10] Intrinsic Evidence: see, e.g., `061, claims 1, 44-48; `061, 5:21-45, 7:26-38; Prosecution History: `061, Paper 20, p. 22.
based on said internal conditions, determining an allowable power consumption level; a computer processor determining a voltage-frequency pair for said allowable power consumption level;
"a computer processor determining a voltage-frequency pair" No construction necessary plain and ordinary meaning. [Term 11] Intrinsic Evidence: See `061 claim 23, Term 7.
"internal conditions of a computer processor" means a plurality of types of operating conditions, excluding core utilization, that are internal to the computer processor. [Term 10] Intrinsic Evidence: `061 patent at Fig. 2; 5:15-45; 5:54-61; 7:26-38; claim 1; `061 File History at Amendment and Response dated July 7, 2003, pp. 19-20, 22, 25-28; Reply to Office Action in Inter Partes Reexamination dated August 27, 2007, pp. 24-27, 31, 33-36. "a computer processor determining a voltage-frequency pair" means a computer processor itself, not the operating system, determines a pair of voltage and frequency values. [Term 11] Intrinsic Evidence: `061 patent at Fig. 2; 3:20-26; 3:47-4:8; 5:21-57; 6:1-40; 7:4053; claim 10; claims 24-27; claim 29; claims 34-38; claims 40-43; claim 53; `061 File History at Amendment and Response dated February 19, 2004, pp. 2-7, 9, 15-17, 23; Reply to Office Action in Inter Partes Reexamination dated August 27, 2007, pp. 20-23, 28-32, 34-35, 40, 42-43, 48-50, 5253.
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`061 Patent
Claim Language Transmeta Proposed Constructions "determining a voltage-frequency pair" No construction necessary plain and ordinary meaning. Intrinsic Evidence: Intel Proposed Constructions "determining a voltage-frequency pair" See '061 claim 15, Term 6.
and dynamically changing power consumption of the computer processor by implementing said voltage-frequency pair, wherein said dynamically changing power consumption comprises changing voltage at which said computer processor is operated while executing instructions in said computer processor. 56. A computing device comprising: a power supply furnishing selectable output voltages; a clock frequency source; and a central processor comprising: a clock frequency generator receiving a clock frequency from the clock frequency source; and a processing unit operable to provide values indicative of operating conditions of the central processor and to cause the power supply and the clock frequency generator to furnish a voltage level and an output clock frequency for the central processor, wherein said processing unit is further operable to cause the power supply to cause voltage furnished to the central
"clock frequency generator" See `061 claim 8, Term 3. Intrinsic Evidence: See `061 claims 57, 58.
"clock frequency generator" See `061 claim 8, Term 3.
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`061 Patent
Claim Language processor to change while the central processor is executing instructions. Transmeta Proposed Constructions Intel Proposed Constructions
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II.
THE `503 PATENT (BELGARD)
`503 Patent
Claim Language 21. A method of calculating physical addresses from virtual addresses, said method comprising: a) calculating a first physical address, having a first page frame field and a first page offset field based on a virtual address; Transmeta Proposed Constructions Intel Proposed Constructions*
"physical address" means a location in the computer's physical, i.e., real, memory. [Term 1] Intrinsic Evidence: see, e.g., `503 Fig. 1,
"physical address" means an address that is sufficient to unambiguously specify the location of a desired unit of data equal in size to the smallest storage location
* Intel's position is that each of the asserted claims of the `503, `733, `668 and `699 patents should be construed to require the use of a memory for storing previously generated "page frame fields" (as construed herein) that is indexed on the basis of virtual address information only. Intrinsic Evidence: '503 patent at Title; Fig. 2A; Fig. 2B; 3:39-48; 3:49-57; 3:58-61; 3:62-64; 5:34-38; 6:8-14; 6:31-38; 6:44-52; 6:53-60; 7:5-16; 7:668:3; 8:59-65; 10:57-67; 11:3-16; 11:34-40; 12:14-21; claims 1-21; '503 File History at Response to Office Action dated October 7, 1996, pp. 1-3; Interview Summary dated March 6, 1997; Amendment and Response to Office Action dated August 4, 1997, p. 12; `466 patent at claims 1-43; '466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated November 24, 1998, pp. 4-8, 10-11; Letter from Applicant dated March 18, 1999, pp. 1-6; Response to Office Action dated March 18, 1999, pp. 5-6; Notice of Allowability dated April 20, 1999 pp. 6-7; '733 patent claim 5; claims 12-16; claims 23-27; claim 31; claim 37; claim 38; '733 File History at Preliminary Amendment dated August 4, 1997, pp. 13-14; Preliminary Amendment For Accompanying Rule 1.60 dated August 4, 1997, pp. 13-14; Amendment and Response dated November 24, 1998, pp. 9-14; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 13-14; Appeals Brief dated March 20, 2000, pp. 11-24, 29-30; Notice of Allowability dated October 5, 2000 pp. 2-10; '668 patent at claim 6; claims 7-15; claim 18; claim 19; '699 File History at Office Action Summary dated August 31, 2001, pp. 3-5; '699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; PTO Office Communication dated March 16, 2004, pp. 3-5. Transmeta objects to Intel's insertion of a general statement about the scope of all of the asserted claims from the `503, `733, `668 and `699 patents. To the extent that Intel believes that specific terms in these patents should be construed to include additional limitations, those limitations should have been set forth in Intel's proposed constructions for specific claim terms. Intel's identification of Intrinsic Evidence regarding a broad statement about the scope of all of the asserted claims is improper and unhelpful. Because this position was not identified by Intel in connection with the parties' exchange of proposed claim constructions, Transmeta reserves the right to rely on any additional intrinsic evidence necessary to rebut this argument during the claim construction briefing, including, for example, the following: `503 File History Application and Paper 13; `466 File History, Paper 5 at pp. 9-12, Paper 8 at pp. 1-5; `733 Fig. 3C, 12:43-49, claim 12, claim 16, claim 17, `733 File History, Paper 4 at pp. 114, Paper 6 at pp. 5-6, Paper 7 at pp. 2-15, Paper 8 at pp. 1-7, Paper 10 at pp. 9-10, Paper 12, Paper 15 at p. 2, Paper 17 at pp. 2-10; `668 File History, Paper 4 at pp. 3-5; `699 File History, 12/15/03 Amendment at pp. 9-12, Office Action dated 3/16/04 at pp. 3-5.
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`503 Patent
Claim Language Transmeta Proposed Constructions Fig. 3A, Fig. 3B, Fig. 3C, 1:11-46, 2:7-15, 8:27-32, 8:41-46, 10:35-38, 10:57-63, 11:3-7; cited references: `554 patent, 1:4156; `836 patent, 3:15-17, 4:61-68, 5:39-43. Intel Proposed Constructions* addressable by the processor, typically one byte. [Term 1] Intrinsic Evidence: `503 patent at Fig. 1; Fig. 3A; Fig. 3B; Fig. 3C; 1:57-58; 2:4-6; 2:47-49; 3:58-67; 5:51-55; 6:2-3; 8:41-45; 8:52-53; 12:34-40; claim 1; claim 7; claim 8; claim 14; claim 15; claim 21; `503 File History at Office Action dated December 7, 1996, pp. 3-4; `466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated August 4, 1997, pp. 4-7, 9; `733 Patent at 13:24; 14:51-53; 15:3-7; 15:6367; 16:29; 16:55-58; claim 17; claim 18; claim 36; claim 73; `733 File History at Preliminary Amendment dated August 4, 1997, pp. 13-14; Amendment and Response dated November 24, 1998 pp. 910; Office Action dated January 19, 1999 at 1-7; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 13-17, 20, 23; Notice of Allowability dated October 5, 2000, pp. 23;'699 patent at claim 1; claim 4;'668 patent claim 1; claim 7; claim 15, claim 17; claim 21; `699 patent claim 1; `699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 1; Fig 2; Fig. 3; Fig. 4;
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`503 Patent
Claim Language Transmeta Proposed Constructions Intel Proposed Constructions* Fig. 5; 2:5-7; 3:3-5; 3:39-42; 5:39-43; 5:58-63; U.S. Patent No. 5,408,626 (incorporated by reference) at 3:15-18. "page frame field" means a portion of a "physical address" sufficient to unambiguously specify the location of a desired page of data. [Term 2] Intrinsic Evidence: `503 patent at Fig. 1; Fig. 2; Fig. 3A; Fig. 3B; Fig. 3C; 2:8-15; 1:63-2:6; 2:43-44; 3:57-67; 5:67-6:1; 6:5361; 8:32-35; 8:51-58; 9:13-20; 10:38-41; 10:57-67; 11:34-40; 11:49-56; `466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; `733 Patent at claims 17-18; claims 22-23; claim 51; `733 File History at Preliminary Amendment For Accompanying Rule 1.60 dated August 4, 1997, p. 13; Amendment and Response dated November 24, 1998, pp. 13-14; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 13, 24, 29; Notice of Allowability dated October 5, 2000, pp. 4, 8; `668 patent claim 1; claim 7; claim 15; claim 17; claim 21;'699 patent claim 1; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 3; Fig. 4; 2:5-7; 5:39-43; 5:58-63; U.S. Patent No. 5,408,626 (incorporated by reference) 3:15-18.
"page frame field" means the portion of a physical address that identifies the physical location of a particular page. A "page" is a block of stored data of predetermined size. [Term 2] Intrinsic Evidence: see, e.g., `503 Fig. 1, Fig. 3A, Fig. 3B, Fig. 3C, 1:63-2:15; 2:4344; 3:57-67; 4:1-6; 5:18-24, 5:63-67; 6:17; 6:53-64; 8:52-57; 8:59-62; 10:57-67; 11:1-7; 11:11-16; 11:34-40; 11:51-61; 12:14-16; cited references: `554 patent, 1:56-59, 2:4-12, 2:62-64, 4:6-8, 4:53-57, 8:61-62; `836 patent, 2:5-7, 5:58-63.
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`503 Patent
Claim Language Transmeta Proposed Constructions Intel Proposed Constructions* "first page frame field" See Intel's construction below at element (d). "first page frame field" No construction necessary plain and ordinary meaning. If the Court decides a construction is necessary, this term means the first referenced page frame field. [Term 4] Intrinsic Evidence: '503 patent at Fig. 3A; Fig. 3B; Fig. 3C, 3:39-64; 11:36-41, "virtual address" means a logical address 12:14-21. having a fixed size and that translates into an intermediate "linear address" (as "virtual address" means an address in a construed herein). [Term 8] segmented address space, the address having a segment identifier and a segment Intrinsic Evidence: '503 patent at offset, and which is translated into a linear Abstract; Title; 1:58-62; 3:36-38; 5:25-34; 5:42-44; 6:4-7; 8:6-12; 9:30-33; 10:19-48; address if paging is enabled, and into a 10:57-63; 11:49-56; claim 9; claim 13; physical address if paging is disabled. '503 File History at Amendment and [Term 8] Intrinsic Evidence: see, e.g., `503 Fig. 1; Response to Office Action dated August 4, 1997, pp. 14-15; '466 File History at Fig. 3A; Fig. 3B; Fig. 3C; 1:11-25; 1:28Preliminary Amendment dated August 4, 36; 1:42-62; 3:36-48; 5:54-56, 7:61-8:12; 1997, pp. 7-8; Amendment and Response 8:27-32, 10:19-34; `503 File History, dated November 24, 1998, pp. 4-5; '733 Paper 12, pp. 14-15; '466 File History, patent at claim 7; claim 20; claim 23; claim Paper 3, pp. 7-8; cited references: `554 patent, 1:24-40, 2:44-52; `836 patent, 1:63- 32; claim 51; claim 69; '733 File History at Preliminary Amendment dated August 4, 65, 3:15-38. 1997, pp. 13-14; Amendment and Response dated November 24, 1998, p. 1011, 13-14; Letter dated June 16, 1999, pp. 1-2; Appeals Brief dated March 20, 2000,
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`503 Patent
Claim Language Intel Proposed Constructions* pp. 7, 9-10, 12-17; 19-24; 29-30; Notice of Allowability dated October 5, 2000, pp. 410; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 2; 3:1519; 3:22-23. "storing/stored" No construction "storing/stored" means storing the page necessary plain and ordinary meaning. If frame for the current memory request in a the Court decides a construction is memory that indexed by virtual address necessary, this term means placing/placed information so that it can be rapidly in storage. [Term 9] accessed to generate a "fast physical Intrinsic Evidence: see, e.g., `503 3:58address" (as construed herein) in response 67; 4:38-40; 6:44-52; 7:3-4; 8:41-46; 9:21- to the next request for data in the segment 24; 10:63-67; 11:1-2; 11:41-44; 12:14-16; from which data is currently being 12:58-62; `503 File History, Paper 12, pp. requested. [Term 9] 14; Paper 4, pp. 2; `466 File History, Paper Intrinsic Evidence: '503 patent at Title; 5, pp. 6; `733 File History, Paper 7, pp. 11; Fig. 2A; Fig. 2B; 3:39-48; 3:58-61; 3:62Paper 17, pp. 5. 64; 5:34-38; 6:8-14; 6:31-38; 6:44-52; 6:53-60; 7:5-16; 7:66-8:3; 8:59-65; 10:5767; 11:3-16; 11:34-40; 12:14-21; claims 121; '503 File History at Response to Office Action dated October 7, 1996, pp. 1-3; Interview Summary dated March 6, 1997; Amendment and Response to Office Action dated August 4, 1997, p. 12; `466 patent at claims 1-43; '466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated November 24, 1998, pp. 4-8, 10-11; Letter from Applicant dated March 18, 1999, pp. 1-6; Response to Office Action dated March 18, 1999, pp. 5-6; Notice of Transmeta Proposed Constructions
b) storing said first page frame field of said first physical address;
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Claim Language Transmeta Proposed Constructions Intel Proposed Constructions* Allowability dated April 20, 1999, pp. 6-7; '733 patent claim 5; claims 12-16; claim 23; claim 27; claim 31; claim 37; claim 38; '733 File History at Preliminary Amendment dated August 4, 1997, pp. 1314; Preliminary Amendment For Accompanying Rule 1.60 dated August 4, 1997, pp. 13-14; Amendment and Response dated November 24, 1998, pp. 911, 13-14; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 13-14; Appeals Brief dated March 20, 2000, pp. 11-24, 29-30; Notice of Allowability dated October 5, 2000 pp. 2-10; '668 patent at claim 6; claims 7-15; claim 18; claim 19; '688 File History at Office Action Summary dated August 31, 2001, pp. 3-5; '699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; '699 PTO Office Communication dated March 16, 2004, pp. 3-5.
c) calculating a second physical address based on a second virtual address including a second page frame field and a second page offset field; d) generating a third physical address based on the first page frame field and the second page offset field;
"third physical address" No construction necessary plain and ordinary meaning. If the Court decides a construction is necessary, this term means the third referenced physical address. [Term 10]
"third physical address" means an address sufficient to unambiguously specify the location of a unit of data equal in size to the smallest storage location addressable by the processor that may or
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`503 Patent
Claim Language Transmeta Proposed Constructions Intrinsic Evidence: see, "physical address," `503 Claim 1, Term 1. Intel Proposed Constructions* may not be the desired unit of data, and which is generated quicker than a "physical address" (as construed herein). [Term 10] Intrinsic Evidence: `503 patent at Fig. 1; Fig 2A; Fig. 2B; Fig. 3A; Fig. 3B; Fig. 3C; 3:49-57; 3:58-67; 6:31-38; 7:5-16; 8:4145; 8:52-53; 8:59-65; 9:2-6; 9:9-13; 9:1621; 10:57-67; 11:3-16; 11:34-40; claim 1; claim 7; claim 8; claim 14; claim 15; claim 21; `503 File History at Office Action dated December 7, 1996, pp. 1-3; Office Action dated December 7, 1996, p.4; `466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated November 24, 1998, pp. 4-7, 9; `733 patent at claim 9; claim 11; claims 17-19; claims 22-23; claim 30; claim 34; claim 36; claim 39; claim 59; claim 63; claim 65; claim 71; claim 73; `668 patent at claim 1; claim 7; claim 15; claim 17; claim 21; `733 File History at Preliminary Amendment dated August 4, 1997, pp. 13-14; Preliminary Amendment For Accompanying Rule 1.60 dated August 4, 1997, p. 13; Amendment and Response dated November 24, 1998, pp. 910; Office Action dated January 19, 1999 at 1-7; Letter dated June 16, 1999, pp. 1-2, Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March
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`503 Patent
Claim Language Transmeta Proposed Constructions Intel Proposed Constructions* 20, 2000, pp. 12-16, 20-24, 29; Notice of Allowability dated October 5, 2000, pp. 23; `668 patent at claim 1; claim 7; claim 15; claim 17; claim 21; `699 patent at claim 1; claim 4; `699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; `U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 1; Fig 2; Fig. 3; Fig. 4; Fig. 5; 2:57; 3:3-5; 3:39-42; 5:39-43; 5:58-63; U.S. Patent No. 5,408,626 (incorporated by reference) at 3:15-18. "based on" means the fast page offset" (as construed herein) is concatenated with a "fast page frame" (as construed herein) to generate a "fast physical address" (as construed herein). [Term 7] Intrinsic Evidence: '503 patent at Fig. 1A, Fig. 3A; Fig. 3B; Fig. 3C; 3:57-67; 8:29-40; 8:51-58; 9:16-21; 19:57-67; 11:34-40; 11: 49-56; '733 patent at claim 4; claim 17; claim 18; claim 23; claim 36; claim 53; claim 59; claim 65; claim 71; '733 File History at Amendment and Response dated November 24, 1998, pp. 910; Amendment and Response to Office Action dated July 30, 1999, p. 9; Letter dated June 16, 1999, pp. 1-2; Appeals Brief dated March 20, 2000, p. 24; Notice of Allowability dated October 5, 2000, p.
"based on" No construction necessary plain and ordinary meaning. If the Court decides a construction is necessary, this term means "using." [Term 7] Intrinsic Evidence: see, e.g., `503 Fig. 1, Fig. 3A, Fig. 3B, Fig. 3C, 3:58-4:6, 5:30-6:7, 11:51-56.
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`503 Patent
Claim Language Transmeta Proposed Constructions Intel Proposed Constructions* 4; '668 patent at claim 1; claim 15; '699 patent at claim 1; '699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 3; Fig. 4; Fig. 5; 2:7-9; U.S. Patent No. 5,408,626 (incorporated by reference) at 3:15-18. "first page frame field" means a "page frame field" (as construed herein) that may or may not be the location of the desired page of data and that is obtained from the "physical address" (as construed herein) used in the previous request for data from the segment from which data is currently being requested. [Term 4] Intrinsic Evidence: '503 patent at Title; Fig. 1; Fig. 2A; Fig. 3A; Fig. 3B; Fig. 3C 3:39-48; 3:49-57; 3:58-61; 3:62-64; 5:3438; 6:8-14; 6:31-38; 6:44-52; 6:53-60; 7:516; 7:66-8:3; 8:59-65; 9:16-21; 10:57-67; 11:3-16; 11:34-40; 12:14-21; claim 1; claims 7-10; claims 13-15; claim 21; '503 File History at Response to Office Action dated October 7, 1996, pp. 1-3; Interview Summary dated March 6, 1997; `466 patent at claims 1-43; '466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated November 24, 1998, pp. 5-8, 10-11;
"first page frame field" See Transmeta's construction above in element (a).
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`503 Patent
Claim Language Transmeta Proposed Constructions Intel Proposed Constructions* Letter from Applicant dated March 18, 1999, pp. 1-6; Response to Office Action dated March 18, 1999, pp. 5-6; `466 Notice of Allowability dated April 20, 1999, pp. 6-7; '733 patent claim 5; claims 12-16; claims 17-18; claim 23; claim 31; claim 37; claim 38; '733 File History at Preliminary Amendment For Accompanying Rule 1.60 dated August 4, 1997, p. 13; Amendment and Response dated November 24, 1998, pp. 13-14; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 11-24, 29; Notice of Allowability dated October 5, 2000, pp. 4, 8; '668 File History at Office Action Summary dated August 31, 2001, pp. 3-5; '668 patent at claim 1; claim 6; claims 714; claim 15; claims 17-18; claim 19; claim 21; '699 patent at claim 1; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 2; Fig. 3; Fig. 4; Fig. 5; 2:5-7; 5:39-43; 5:58-63; U.S. Patent No. 5,408,626 (incorporated by reference) at 3:15-18; '699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; '699 PTO Office Communication dated March 16, 2004, pp. 3-5. "memory access request based on said third physical address" means using said
e) generating a memory access request based on said third physical address;
"memory access request based on said third physical address" No construction
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`503 Patent
Claim Language Transmeta Proposed Constructions necessary plain and ordinary meaning. If the Court decides a construction is necessary, this term means using the third physical address to locate data in memory. [Term 11] Intrinsic Evidence: `503 4:1-15, 7:16-19, 8:29-9:45, 11:33-12:3. Intel Proposed Constructions* "third physical address" (as construed herein) to access memory in the same manner as if the final fully translated full physical address" (as construed herein) was already available. [Term 11] Intrinsic Evidence: `503 patent at Fig. 1; Fig 3A; Fig. 3B; Fig. 3C; 8:34-39; 8:4151; 9:16-21; 9:21-24; 10:57-67; 11:34-40; 12:14-21; claim 9; claim 13;'466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated November 24, 1998, pp. 10-11; `733 Patent at claim 2; claim 7; claim 13; claim 20; claim 24; claim 29; claim 41; claim 44 ; claim 49; claim 52; claim 58; claim 64; claim 70; `733 File History at Amendment and Response dated November 24, 1998 pp. 9-10; Office Action dated January 19, 1999 at 1-7; Letter dated June 16, 1999, p. 1; Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 12-13.
(f) canceling said access request to memory using said third physical address if the first page frame field is not equal to the second page frame field of said second physical address. 22. The method of claim 21, wherein the page frame fields most recently used by "page frame fields most recently used by "page frame field[] most recently used the computer system" No construction by the computer system" means a "page
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`503 Patent
Claim Language the computer system are stored. Transmeta Proposed Constructions necessary plain and ordinary meaning. If the Court decides a construction is necessary, this term means page frame fields used in one or more most recent previous requests. [Term 12] Intrinsic Evidence: see, e.g., `503 Fig. 3A, Fig. 3B, Fig. 3C, 3:30-32, 3:58-67, 6:44-64, 7:3-19, 7:29-33, 8:52-65, 10:5711-18. Intel Proposed Constructions* frame field" (as construed herein) that may or may not be the location of the desired page of data and that is obtained from the physical address" (as construed herein) used in the previous request for data from the segment from which data is currently being requested. [Term 12] Intrinsic Evidence: '503 patent at Title; Fig. 1; Fig. 2A; Fig. 3A; Fig. 3B; Fig. 3C 3:39-48; 3:49-57; 3:58-61; 3:62-64; 5:3438; 6:8-14; 6:31-38; 6:44-52; 6:53-60; 7:516; 7:66-8:3; 8:59-65; 9:16-21; 10:57-67; 11:3-16; 11:34-40; 12:14-21; claim 1; claims 7-10; claims 13-15; claim 21; '503 File History at Response to Office Action dated October 7, 1996, pp. 1-3; Interview Summary dated March 6, 1997; `466 patent at claims 1-43; '466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated November 24, 1998, pp. 5-8, 10-11; Letter from Applicant dated March 18, 1999, pp. 1-6; Response to Office Action dated March 18, 1999, pp. 5-6; `466 Notice of Allowability dated April 20, 1999, pp. 6-7; '733 patent claim 5; claims 12-16; claims 17-18; claim 23; claim 31; claim 37; claim 38; '733 File History at Preliminary Amendment For Accompanying Rule 1.60 dated August 4, 1997, p. 13; Amendment and Response
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Claim Language Transmeta Proposed Constructions Intel Proposed Constructions* dated November 24, 1998, pp. 13-14; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 11-24, 29; Notice of Allowability dated October 5, 2000, pp. 4, 8; '668 File History at Office Action Summary dated August 31, 2001, pp. 3-5; '668 patent at claim 1; claim 6; claims 714; claim 15; claims 17-18; claim 19; claim 21; '699 patent at claim 1; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 2; Fig. 3; Fig. 4; Fig. 5; 2:5-7; 5:39-43; 5:58-63; U.S. Patent No. 5,408,626 (incorporated by reference) at 3:15-18; '699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; '699 PTO Office Communication dated March 16, 2004, pp. 3-5
23. The method of claim 21, further including a step: checking whether the first page frame field can be used for an address translation.
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`733 Patent
Claim Language 1. A system for performing address translations usable by a processor employing both segmentation and optional independent paging the system comprising: Transmeta Proposed Constructions "segmentation" means a form of memory management where a virtual address space is divided into segments, where each segment is allowed to start at any boundary, and have any length.* [Term 13] Intrinsic Evidence: see, e.g., `503 Fig. 1, Fig. 3A, Fig. 3B, Fig. 3C, 1:47-62, 2:36-49, 5:25-50, 6:25-29; Prosecution History, `733 Paper 10, pp.910, Paper 14, pp.8-14; U.S. Patent No. 5,321,836 (incorporated by reference) at 3:46-51; cited references: `554 patent, 1:57-65, 2:44-52; `836 patent, 1:63-65, 3:15-38, 3:46-51. Intel Proposed Constructions "segmentation" means the process of converting a "virtual address" (as construed herein) to a "linear address" (as construed herein). [Term 13] Intrinsic Evidence: `503 patent at Title; claim 9; claim 13; `503 File History at Amendment and Response to Office Action dated August 4 1997, pp. 14-15; `466 File History at Amendment and Response dated November 24, 1998, pp. 4-5; `733 Patent claim 32; `733 File History at Preliminary Amendment dated August 4, 1997, pp. 13-14; Preliminary Amendment For Accompanying Rule 1.60 dated August 4, 1997, pp. 13-14; Amendment and Response dated November 24, 1998, pp. 11, 13-14; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 9-10, 13-14; Appeals Brief dated March 20, 2000, pp. 7, 9-10, 12-17, 19-24, 29-30; Notice of Allowability dated October 5, 2000, pp. 4-10; U.S. Patent No. 5,321,386 (incorporated by reference) at 3:15-19; 3:22-23.
* Transmeta's position is that construed preamble terms are limitations. Intel does not adopt this position.
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`733 Patent
Claim Language Transmeta Proposed Constructions "optional independent paging" means a form of memory management which can be enabled or disabled, and where the physical memory is divided into pages of predetermined size, which pages may be located independent of segment boundaries and lengths.* [Term 14] Intrinsic Evidence: see, e.g., `503 Fig. 3A, Fig. 3B, Fig. 3C, 2:16-22, 2:36-59, 7:22-28, 9:61-63; cited references: `836 patent, 3:19-21, 3:43-4:6. Intel Proposed Constructions "optional independent paging" means the optional process of converting a "linear address" (as construed herein) to a "physical address" (as construed herein) following the completion of "segmentation" (as construed herein). [Term 14] Intrinsic Evidence: `503 patent at 5:25-29; 6:4-7; 6:31-36; 7:7-10; 10:35-38; claim 1; claim 7; claim 8; claim 9; `503 File History at Amendment and Response to Office Action dated August 4, 1997, pp. 14-15; Amendment and Response dated November 24, 1998, pp. 4-5; `466 File History at Preliminary Amendment dated August 4, 1997, pp. 7-8; `733 patent at claim 32; `733 File History at Preliminary Amendment dated August 4, 1997, pp. 13-14; Preliminary Amendment For Accompanying Rule 1.60 dated August 4, 1997, pp. 13-14; Amendment and Response dated November 24, 1998, pp. 11, 13-14; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 9-10, 13-14; Appeals Brief dated March 20, 2000, pp. 7, 9-10, 12-17, 19-24, 29-30; Notice of Allowability dated October 5, 2000, pp. 4-10; U.S. Patent No. 5,321,386 (incorporated by reference) at 3:19-21; 3:39-42.
* Transmeta's position is that construed preamble terms are limitations. Intel does not adopt this position.
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`733 Patent
Claim Language Transmeta Proposed Constructions Intel Proposed Constructions
means for generating an actual physical address from a virtual address in a time period T, said virtual address having both a segment identifier and a segment offset by calculating a linear address based on said entire virtual address, and by calculating said actual physical address based on said calculated linear address; and
"means for generating an actual physical address from a virtual address . . . by calculating a linear address based on said entire virtual address, and by calculating said actual physical address based on said calculated linear address" is a means-plus-function limitation that must be construed according to 35 U.S.C. §112, ¶ 6. [Term 15] [Agreed-to term] Function: The function performed by the claimed "means for generating" is generating a non-speculative physical address from a virtual address in a time period T, said virtual address having both a segment identifier and a segment offset by calculating a linear address based on said entire virtual address, and by calculating said actual physical address based on said calculated linear address. Structure: The disclosed structure that corresponds to the function of the claimed "means for generating" is an adder 305, a page cache 307, and register portion 291 or 391. (See Fig. 3B and 3C). "actual physical address" means a nonspeculative physical address. [Term 16] Intrinsic Evidence: see, e.g., `503 Fig. 1, Fig. 3A, Fig. 3B, Fig. 3C, 1:11-25; 1:42-46; 1:51-62; 2:7-15, 3:61-67; 4:11-15; 7:8-11, 8:27-34; 9:3045; 10:35-38; 10:57-63; 11:3-7; 11:33-12:8; Prosecution History: `733, Paper 14, pp. 8. "actual physical address" means an address that is sufficient to unambiguously specify the location of a desired unit of data equal in size to the smallest storage location addressable by the processor, typically one byte. [Term 16] Intrinsic Evidence: `503 patent at Fig. 1; Fig. 3A; Fig. 3B; Fig. 3C; 1:57-58; 2:4-6; 2:47-49; 3:58-67; 5:51-55; 6:2-3; 8:41-45; 8:52-53; 12:3440; claim 1; claim 7; claim 8; claim 14; claim 15; claim 21; `503 File History at Office Action dated
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`733 Patent
Claim Language Transmeta Proposed Constructions Intel Proposed Constructions December 7, 1996, pp. 3-4; `466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated August 4, 1997, pp. 4-7, 9; `733 Patent at 13:24; 14:51-53; 15:3-7; 15:63-67; 16:29; 16:55-58; claim 17; claim 18; claim 36; claim 73; `733 File History at Preliminary Amendment dated August 4, 1997, pp. 13-14, Amendment and Response dated November 24, 1998, pp. 9-10; Office Action dated January 19, 1999 at 1-7; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 13-17, 20, 23; Notice of Allowability dated October 5, 2000, pp. 2-3; `699 patent at claim 1; claim 4;'668 patent claim 1; claim 7; claim 15, claim 17; claim 21; `699 patent claim 1; `699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 1; Fig 2; Fig. 3; Fig. 4; Fig. 5; 2:5-7; 3:3-5; 3:39-42; 5:39-43; 5:58-63; U.S. Patent No. 5,408,626 (incorporated by reference) at 3:15-18. "virtual address" See `503 claim 21, Term 8. "segment identifier" means the portion of a virtual address that identifies a segment in the virtual address space. [Term 17] Intrinsic Evidence: see, e.g., `503 Fig 1, Fig. 3A, Fig. 3B, Fig. 3C (segment identifier 301a), 1:5155, 3:36-48, 5:3-7, 5:30-41, 6:25-29; Prosecution "segment identifier" means the component of a "virtual address" (as construed herein) that uniquely identifies a variable-sized portion of data in a memory management system. [Term 17] Intrinsic Evidence: `503 patent 3:36-48; 5:1-17;
"virtual address" See `503 claim 21, Term 8.
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`733 Patent
Claim Language Transmeta Proposed Constructions History: `733, Paper 10, pp. 9-10; Paper 14, pp. 23. Intel Proposed Constructions 5:30-41; 7:66-8:12; 10:19-34; claim 9; claim 13; `503 File History at Amendment and Response to Office Action dated November 24, 1998, pp. 1415'733 patent at claim 1; claim 6; claim 12; claims 17-19; claim 28; claim 36; claim 44; claim 48; claim 51; claim 57; claim 63; claim 69; `733 File History at Amendment and Response dated November 24, 1998, pp. 9-10; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 20, 24; Notice of Allowability dated October 5, 2000, pp. 2-10; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 2; 3:24-27; 4:61-65. "segment offset" means the component of a "virtual address" (as construed herein) that is added to a base address to calculate a "linear address" (as construed herein). [Term 18] Intrinsic Evidence: `503 patent at 5:42-50; 8:669:13; 11:19-32; `503 File History at Office Action dated December 7, 1996, p. 5; Amendment and Response to Office Action dated August 4 1997, pp. 14-15; `733 patent at claim 1; claim 6; claim 12; claims 17-19; claim 23; claim 28; claim 36; claim 44; claim 48; claim 51; `733 File History at Amendment and Response dated November 24, 1998, pp. 9-10; Letter dated June 16, 1999, pp. 12; Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 20, 24; Notice of Allowability dated October 5,
"segment offset" means the portion of a virtual address that identifies a location within a segment. [Term 18] Intrinsic Evidence: see, e.g., `503 Fig. 1, Fig. 3A, Fig. 3B, Fig. 3C (segment offset 301b), 1:5158, 3:36-38, 5:3-7, 5:42-50, 8:13-26; Prosecution History: `733, Paper 10, pp. 9-10; Paper 14, pp. 23.
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`733 Patent
Claim Language Transmeta Proposed Constructions Intel Proposed Constructions 2000, pp. 2-10; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 2; 3:24-27; 3:30-32; 4:61-65. "linear address" means a logical address having a fixed size and that translates into an actual "physical address" (as construed herein). [Term 19] Intrinsic Evidence: `503 patent at Abstract; 1:5862; 3:36-38; 5:25-34; 5:42-44; 6:4-7; 8:6-12; 9:3033; 10:19-48; 10:57-63; 11:49-56; claim 9; claim 13; `503 File History at Amendment and Response to Office Action dated August 4 1997, pp. 14-15; `466 File History at Preliminary Amendment dated August 4 1997, pp. 7-8; Amendment and Response dated November 24, 1998, pp. 4-5; `733 patent at claim 7; claim 20; claim 23; claim 32; claim 51; claim 69; `733 File History at Amendment and Response dated November 24, 1998, p. 10; Appeals Brief dated March 20, 2000, p. 12; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 2; Fig. 3; 4:61-65; U.S. Patent No. 5,408,626 (incorporated by reference) at 3:5764; 4:3-8; 4:22-24. "fast physical address" means an address sufficient to unambiguously specify the location of a unit of data equal in size to the smallest storage location addressable by the processor that may or may not be the desired unit of data, and which is generated quicker than a "physical address" (as construed herein). [Term 20]
"linear address" means an address identifying a location in a continuous unsegmented address space, which is translated from a virtual address, and which is translated into a physical address. [Term 19] Intrinsic Evidence: see, e.g., `503 Fig. 1, Fig. 3A, Fig. 3B, Fig. 3C, 1:58-2:6, 3:36-48, 5:25-29, 5:42-6:7, 8:13-29; cited references: `554 patent, 2:44-67, 3:60-4:8; `836 patent, 1:63-65, 3:22-38.
a fast physical address generator for generating a fast physical address related to said virtual address in a time
"fast physical address" means an address specifying the location of data that may or may not be the desired location, and which is available sooner than an actual physical address. [Term 20] Intrinsic Evidence: see, e.g., `503 Fig. 3A, Fig. 3B, Fig. 3C (fast physical address 303), 4:1-15, 7:10-19, 8:52-9:59, 11:33-12:26; `733 Abstract;
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Claim Language Transmeta Proposed Constructions Prosecution History: `733, Paper 14, pp. 12, 27; `699 Paper 5, p. 9. Intel Proposed Constructions Intrinsic Evidence: `503 patent at Fig. 1; Fig 2A; Fig. 2B; Fig. 3A; Fig. 3B; Fig. 3C; 3:49-57; 3:5867; 6:31-38; 7:5-16; 8:41-45; 8:52-53; 8:59-65; 9:2-6; 9:9-13; 9:16-21; 10:57-67; 11:3-16; 11:3440; claim 1; claim 7; claim 8; claim 14; claim 15; claim 21; `503 File History at Office Action dated December 7, 1996, pp. 1-3; Office Action dated December 7, 1996, p.4; `466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated November 24, 1998 pp. 4-7, 9; `733 patent at claim 9; claim 11; claims 17-19; claims 22-23; claim 30; claim 34; claim 36; claim 39; claim 59; claim 63; claim 65; claim 71; claim 73; `668 patent at claim 1; claim 7; claim 15; claim 17; claim 21; `733 File History at Preliminary Amendment dated August 4, 1997, pp. 13-14; Preliminary Amendment For Accompanying Rule 1.60 dated August 4, 1997, p. 13; Amendment and Response dated November 24, 1998, pp. 9-10; Office Action dated January 19, 1999 at 1-7; Letter dated June 16, 1999, pp. 1-2, Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 12-16, 20-24, 29; Notice of Allowability dated October 5, 2000, pp. 2-3; `699 patent at claim 1; claim 4; `699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; `U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 1; Fig 2; Fig. 3; Fig. 4; Fig. 5; 2:5-7; 3:3-5; 3:3942; 5:39-43; 5:58-63; U.S. Patent No. 5,408,626
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Claim Language Transmeta Proposed Constructions Intel Proposed Constructions (incorporated by reference) at 3:15-18. "generating a memory access" means using a "fast physical address" (as construed herein) to access memory in the same manner as if the final fully translated full "physical address" (as construed herein) was already available. [Term 21] Intrinsic Evidence: `503 patent at Fig. 1; Fig 3A; Fig. 3B; Fig. 3C; 8:34-39; 8:41-51; 9:16-21; 9:2124; 10:57-67; 11:34-40; 12:14-21; claim 9; claim 13;'466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated November 24, 1998, pp. 10-11; `733 Patent at claim 2; claim 7; claim 13; claim 20; claim 24; claim 29; claim 41; claim 44 ; claim 49; claim 52; claim 58; claim 64; claim 70; `733 File History at Amendment and Response dated November 24, 1998, pp. 9-10; Office Action dated January 19, 1999 at 1-7; Letter dated June 16, 1999, p. 1; Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 12-13.
2. The system of claim 1, wherein the fast physical address can be used for generating a memory access faster than a memory access based on said actual physical address.
"generating a memory access" No construction necessary plain and ordinary meaning. If the Court decides a construction is necessary, this term means using an address to locate data in memory. [Term 21] Intrinsic Evidence: see, e.g., `503 4:1-15, 7:1619, 8:29-9:45, 11:33-12:3.
3. The system of claim 2, including a cancellation circuit for cancelling the memory access if the fast physical address and actual physical address are different.
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Claim Language 4. The system of claim 1, wherein the fast physical address is generated based on a combination of physical address information from a different virtual address, and partial linear address information relating to said virtual address. Transmeta Proposed Constructions "combination/combined/combining" means association/associated/associating. [Term 22] Intrinsic Evidence: see, e.g., `503 4:1-10, 8:2026, 9:14-29, 11:33-44. Intel Proposed Constructions "combination/combined/combining" means . . . the fast page offset" (as construed herein) is concatenated with a "fast page frame" (as construed herein) to generate a "fast physical address" (as construed herein). [Term 22] Intrinsic Evidence: '503 patent at Fig. 1A, Fig. 3A; Fig. 3B; Fig. 3C; 3:57-67; 8:29-40; 8:51-58; 9:16-21; 19:57-67; 11:34-40; 11: 49-56; '733 patent at claim 4; claim 17; claim 18; claim 23; claim 36; claim 53; claim 59; claim 65; claim 71; '733 File History at Amendment and Response dated November 24, 1998, pp. 9-10; Amendment and Response to Office Action dated July 30, 1999, p. 9; Letter dated June 16, 1999, pp. 1-2; Appeals Brief dated March 20, 2000, p. 24; Notice of Allowability dated October 5, 2000, p. 4; '668 patent at claim 1; claim 15; '699 patent at claim 1; '699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; U.S. Patent No. 5,321,836 (incorporated by reference) at Fig. 3; Fig. 4; Fig. 5; 2:7-9; U.S. Patent No. 5,408,626 (incorporated by reference) at 3:15-18. "physical address information from a different virtual address" means a "page frame field" (as construed herein) that may or may not specify the location of the desired page of data and that is obtained from the "physical address" (as construed herein) used in the previous request for data from the segment from which data is currently being
"physical address information from a different virtual address" No construction necessary plain and ordinary meaning. If the Court decides a construction is necessary, this term means at least a portion of a physical address translated from a prior virtual address. [Term 23] Intrinsic Evidence: see, e.g., `503 Fig. 3A, Fig.
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Claim Language Transmeta Proposed Constructions 3B, Fig. 3C (last page frame 397), 3:58-4:10, 4:16-26, 6:47-64, 7:3-19, 8:52-9:45, 10:63-11:18. Intel Proposed Constructions requested. [Term 23] Intrinsic Evidence: '503 patent at Title; Fig. 1; Fig. 2A; Fig. 3A; Fig. 3B; Fig. 3C;3:39-48; 3:4957; 3:58-61; 3:62-64; 5:34-38; 6:8-14; 6:31-38; 6:44-52; 6:53-60; 7:5-16; 7:66-8:3; 8:59-65; 9:1621; 10:57-67; 11:3-16; 11:34-40; 12:14-21; claim 1; claims 7-10; claims 13-15; claim 21; '503 File History at Response to Office Action dated October 7, 1996, pp. 1-3; Interview Summary dated March 6, 1997; `466 patent at claims 1-43; '466 File History at Preliminary Amendment dated August 4, 1997, pp. 2-8; Amendment and Response dated November 24, 1998, pp. 5-8, 1011; Letter from Applicant dated March 18, 1999, pp. 1-6; Response to Office Action dated March 18, 1999, pp. 5-6; `466 Notice of Allowability dated April 20, 1999, pp. 6-7; `733 patent claim 5; claims 12-16; claims 17-18; claim 23; claim 31; claim 37; claim 38; '733 File History at Preliminary Amendment For Accompanying Rule 1.60 dated August 4, 1997, p. 13; Amendment and Response dated November 24, 1998, pp. 13-14; Letter dated June 16, 1999, pp. 1-2; Amendment and Response dated July 30, 1999, pp. 9-10; Appeals Brief dated March 20, 2000, pp. 11-24, 29; Notice of Allowability dated October 5, 2000, pp. 4, 8; '668 File History at Office Action Summary dated August 31, 2001, pp. 3-5; '668 patent at claim 1; claim 6; claims 7-14; claim 15; claims 17-18; claim 19; claim 21; '699 patent at claim 1; U.S. Patent No. 5,321,836 (incorporated
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Claim Language Transmeta Proposed Constructions Intel Proposed Constructions by reference) at Fig. 2; Fig. 3; Fig. 4; Fig. 5; 2:5-7; 5:39-43; 5:58-63; U.S. Patent No. 5,408,626 (incorporated by reference) at 3:15-18; '699 File History at Amendment and Response dated December 15, 2003, pp. 9-10; '699 PTO Office Communication dated March 16, 2004, pp. 3-5. "partial linear address information relating to said ...virtual address" means a portion of a "physical address" (as construed herein) sufficient to unambiguously specify the location of a byte of data within a page and that is used together with a "fast page frame" (as construed herein) to form a "fast physical address" (as construed herein). [Term 24] Intrinsic Evidence: `503 patent at Fig. 1A, Fig. 3A; Fig. 3B; F
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