Free Declaration - District Court of Delaware - Delaware

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 1 of 40

IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF DELAWARE LG DISPLAY CO., LTD., Plaintiff, v. CHI MEI OPTOELECTRONICS CORPORATION, et al. Defendants. ) ) ) ) ) ) ) ) ) ) )

Civil Action No. 06-726 (JJF) Civil Action No. 07-357 (JJF) CONSOLIDATED CASES

DECLARATION OF DR. MILTIADIS HATALIS IN SUPPORT OF DEFENDANTS CHI MEI OPTOELECTRONICS' PROPOSED CLAIM CONSTRUCTIONS OF COUNSEL: Jonathan S. Kagan Alexander C.D. Giza Adam Hoffman Irell & Manella LLP 1800 Avenue of the Stars, Suite 900 Los Angeles, California 90067-4276 (310) 277-1010 Dated: August 11, 2008 Philip A. Rovner (#3215) POTTER, ANDERSON & CORROON LLP Hercules Plaza 1313 N. Market St. P.O. Box 951 Wilmington, Delaware 19899-0951 (302) 984-6000 [email protected] Attorneys for Defendant Chi Mei Optoelectronics Corporation

1912933.2

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 2 of 40

IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF DELAWARE LG DISPLAY CO., LTD., Plaintiff, v. CHI MEI OPTOELECTRONICS CORPORATION, et al. Defendants. ) ) ) ) ) ) ) ) ) ) )

Civil Action No. 06-726 (JJF) Civil Action No. 07-357 (JJF) CONSOLIDATED CASES

DECLARATION OF DR. MILTIADIS HATALIS IN SUPPORT OF DEFENDANTS CHI MEI OPTOELECTRONICS' PROPOSED CLAIM CONSTRUCTIONS

I, Dr. Miltiadis Hatalis, declare as follows: I. INTRODUCTION 1. I have been retained as an expert technical witness by Irell & Manella LLP

on behalf of Chi Mei Optoelectronics Corporation and Chi Mei Optoelectronics USA (CMO) in connection with the above-captioned action. In this declaration, I provide technical background information relating to U.S. Patent 4,624,737 (the `737 patent, Exhibit B hereto) and 5,825,449 (the `449 patent, Exhibit C hereto) asserted by LG Display Co. Ltd. ("LGD"), and in particular describe certain aspects of fabricating thin film transistors and liquid crystal displays that make use of them. I also provide opinions on the meaning of certain terms used in the `737 and `449 patents to a person of ordinary skill in the relevant art at the time of the respective effective filing dates of the applications for those patents.

1912933.2

-2-

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 3 of 40

2.

In preparing this submission, I have studied the `737 and `449 patents as well

as their file histories. I have also reviewed the proposed claim constructions set forth in the amended Joint Claim Construction exhibits filed August 6, 2008, for these two patents. II. QUALIFICATIONS 3. I have studied, taught, and practiced in the relevant flat panel display

technology for over 20 years. I received my Doctor of Philosophy (Ph.D.) degree in the field of Electrical and Computer Engineering from Carnegie Mellon University in 1987. The topic of my Ph.D. dissertation research was "Crystallization of Amorphous Silicon Films and its Application in Bipolar and Thin Film Transistors." I received my Masters of Science (M.S.) degree in Electrical and Computer Engineering in 1984 from the State University of New York at Buffalo and my Bachelor of Science (B.S.) degree in Physics in 1982 from the Aristotle University of Thessaloniki in Greece. 4. Upon receiving my Ph.D. degree, I joined the faculty of Lehigh University in

the Department of Electrical and Computer Engineering as an Assistant Professor. I was promoted to the rank of Associate Professor with tenure in 1991 and to the rank of Professor in 1995. From 1987-1992, I served as Associate Director of Lehigh's "Microelectronics Research Laboratory." In 1992, I founded and became Director of the "Display Research Laboratory," which was the first academic laboratory in the United States dedicated to research and development of Thin Film Transistors (TFTs) for Active Matrix Liquid Displays (AMLCDs) and Active Matrix Organic Light Emitting Diode (AMOLEDs) displays. As Director of Lehigh's "Display Research Laboratory," I have raised over $10 million through research contracts and grants to support the laboratory's research and development activities on thin film transistors and their application to flat panel displays.
1912933.2

-3-

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 4 of 40

These contracts and grants were awarded by the Defense Advanced Research Program Agency (DARPA), the Army Research Laboratory (ARL), the National Science Foundation (NSF), the National Aeronautics and Space Administration (NASA), the State of Pennsylvania and a variety of industrial companies including IBM, Kodak, Sharp, Northrop Grumman, and others. 5. As a faculty member, I supervised the research of over a dozen Ph.D.

dissertations in the technical field of thin film transistors and, along with my graduate students, published over 100 technical publications in scientific journals or conferences in the field of thin film transistors and their application in flat panel displays. In addition to the aforementioned Ph.D. dissertations, I have also supervised a large number of graduate student master's theses and undergraduate projects. I have taught a number of different undergraduate and graduate level courses in the Electrical and Computer Engineering department at the Lehigh University dealing with the physics, technology and the design of solid-state devices and circuits. I have also introduced and regularly teach a course on "Semiconductor Material and Device Characterization," and I have also reorganized a twocourse sequence on Design of Very Large Scale Integration (VLSI) which are "Introduction to VLSI Circuits" and "Introduction to VLSI Systems." 6. My research pioneered the low temperature crystallization of amorphous

silicon for producing polycrystalline silicon (polysilicon) thin film transistors, as well as the application of these devices to a number of novel circuits for integrated display drivers and their use for fabrication of AMLCD and AMOLED displays. Currently, my research group is investigating the development to flexible displays. We recently presented what we believe to be the world's first VGA flexible Active Matrix Display using polysilicon TFTs.

1912933.2

-4-

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 5 of 40

7.

As part of my research, I utilize much of the same equipment and many of

the same microfabrication processes that are relevant to the `449 and `737 Patents, including: Plasma Enhanced Chemical Vapor Deposition (PECVD) for intrinsic hydrogenated-amorphous silicon, silicon nitride and silicon dioxide films; sputter and ebeam deposition tools for aluminum, indium-tin-oxide, tantalum and other metallic thin films; photolithographic tools for spinning, exposing and developing photoresist patterns; as well as plasma or wet etching processes for removing various thin film materials from the substrate. I also utilize a variety of electrical characterization techniques and instruments for testing the electrical performance of completed TFT circuits and flat panel displays. 8. As part of my research, I pioneered a technique for crystallizing amorphous

silicon. The technique I pioneered has been used in the manufacture of small polysilicon TFT AMLCDs for over a dozen years, and, more recently, polysilicon TFTs have also been used for the manufacture of AMOLED displays. In addition, many industrial and academic laboratories have recently initiated R&D activities related to the fabrication of polysilicon thin film transistors on flexible metal foil substrates and their application to flexible displays. Such research flows from the accomplishments of my research group in this technical field. 9. My industrial experience includes work at the XEROX Palo Alto Research

Laboratory and various consulting projects with flat panel display companies as well as companies producing equipment for the manufacture of flat panel displays. All of these projects were related to the thin film transistors and their application to flat panel displays. 10. I am a member of several professional organizations including the Society for

Information Displays (SID), and the Electron Device Society of the Institute of Electrical
1912933.2

-5-

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 6 of 40

and Electronics Engineers (IEEE). I have been the chair or co-chair at numerous national and international conferences/symposiums including several SID sponsored Workshops on Active Matrix Liquid Crystal Displays and a Materials Research Society Symposium on Flat Panel Displays. I have co-authored two book chapters, one dealing with the "Polysilicon TFT Technology" and another on application of "Polysilicon TFTs in AMOLED Displays." I have served as a reviewer for technical papers submitted to several scientific journals and have also served as a reviewer for several years for the National Science Foundation Small Business Innovative Research (SBIR) program. My latest curriculum vitae, which includes a list of my publications in scientific journals and conferences, is attached at Exhibit A. III. CLAIM CONSTRUCTION STANDARDS 11. I understand that in construing patent claims, courts seek to determine what a

person of ordinary skill in the art would understand the claims to mean primarily in light of the intrinsic evidence of record, including the written description, the drawings, and the prosecution history. In particular, I understand that the patent specification is considered the single best guide to the meaning of a particular claim term. 12. I also understand that, in general, claim language should be given its ordinary

and customary meaning as would be understood by one of ordinary skill in the art at the time of the invention. An exception to this general rule is where a patentee defines his own terms, giving a claim term a different meaning than the term would otherwise possess, or expressly disclaims or disavows the full claim scope. In these situations, the inventor's lexicography governs. Also, the specification may resolve ambiguous claim terms where the ordinary and accustomed meaning of the words used in the claims lacks sufficient clarity to permit the scope of the claim to be ascertained from the words alone.

1912933.2

-6-

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 7 of 40

13.

I further understand that when courts look to the specification for clarification

of ambiguous claim terms, courts still must avoid reading unclaimed limitations appearing in the specification into the claims. Moreover, I understand that courts may occasionally consider supplemental resources such as dictionaries, encyclopedias, and treatises to assist in determining the ordinary and customary meanings of claim terms. 14. In my opinion, "a person of ordinary skill in the art" for the technology of the

`737 and `449 patents would have a Bachelor's of Science degree in Electrical Engineering, Physics (with an emphasis in semiconductors or solid state devices), or Materials Science, and at least several years of experience in the design, development and manufacturing of AMLCD or other types of flat panel displays that utilize thin film transistors, or an equivalent combination of education and work experience.

IV.

INTRODUCTION TO THIN FILM TRANSISTORS AND LCD DISPLAYS 15. Thin-film transistors (TFTs) are the building-blocks of Liquid Crystal

Displays (LCD). In a typical LCD, the image is made up of many small elements called pixels, arranged in rows across the display area. The electronic components that control a pixel in a typical LCD include a TFT, a storage capacitor, and a pixel capacitor formed between the pixel electrode and the common display electrode. Both the pixel and the display common electrodes are typically made from a transparent conductive film such an Indium Tin Oxide (ITO). When a voltage is applied to the pixel electrode, the relative rotation of the liquid crystal molecules between the ITO pixel electrode and the common display electrode is affected and this modifies the amount of light that is passing through the pixel.

1912933.2

-7-

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 8 of 40

A. How A TFT Works 16. The TFT serves as a "switch" that controls the amount of voltage to each

pixel electrode, which in turn affects the amount of light that passes through each pixel. When turned on, the TFT allows an electrical current to flow into and charge the storage capacitor to a specific voltage. When the TFT is turned off, current cannot flow through it and thus the voltage established at the capacitor is maintained. The voltage stored in the capacitor appears to the pixel electrode, and thereby determines the amount of light that passes through the pixel. 17. The `449 and `737 patents both concern themselves in significant part with

the fabrication of TFTs. Therefore, I provide additional background information on the structure, manufacture and operation of TFTs. The following is a simplified conceptual diagram of a generic TFT. FIGURE A: Conceptual diagram of a common type of TFT

Source: Mercouri G. Kanatzidis, Semiconductor physics: Quick-set thin films, Nature 428, 269-271 (March 18, 2004) (Exhibit D hereto). 18. As can be seen in the above simplified diagram, a thin film transistor is an

electronic device having three terminals referred to as the "gate," "source" and "drain."
1912933.2

-8-

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 9 of 40

Current flows between the source and drain under control of the gate, through a region referred to as "the channel." More specifically, the current is turned on and off by applying a voltage to the gate. Voltage is applied from an external source to the gate electrode, depicted above generally as the blue region labeled "Gate." The voltage applied to the gate affects the conductive properties of the Thin-film Semiconductor depicted above, which is separated from the gate by an insulating layer (labeled "Insulator"). The thin-film semiconductor is "semi-conductive" ­ that is, it is neither strictly a conductor nor an insulator, but acts alternatively as a conductor or an insulator depending upon the gate voltage. By controlling the amount of voltage to the gate, the flow of current through the semiconductor between the source and the drain can be controlled. In this way, the TFT can be used as an "on/off" switch. 19. Critical to the operation of the TFT is the aforementioned "channel." The

channel in the earlier diagram is the region in the thin-film semiconductor material between the source and drain electrodes and right above the interface with the gate insulator, where electricity is conducted when the TFT is "on." The channel is conceptually depicted in the previous diagram as red arrows from the source to the drain. B. Structure of a TFT 20. As reflected in the earlier illustration, a TFT is generally built on top of a

substrate, usually some kind of insulator such as glass. In a typical process for building such a TFT, the gate electrode is first formed on top of the substrate. The gate electrode is usually a conductor, such as a metal. Next, an insulator is formed on top of the gate electrode. The insulator serves to electrically isolate the gate from the source and drain electrodes and from the thin-film semiconductor containing the channel. Next, a thin-film
1912933.2

-9-

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 10 of 40

semiconductor is formed on top of the insulator. As noted above, the semiconductor can act as a conductor or an insulator, depending on the voltage applied to the gate. 21. Relating the above description to the terminology used in the `737 patent, the

function of the Substrate shown in the diagram is generally performed by the "insulating substrate" illustrated in the `737 patent. The function of the Gate in the diagram is generally performed by the "gate electrode" illustrated in the `737 patent. The function of the Insulator in the diagram is generally performed by the "gate insulating film" illustrated in the `737 patent. Finally, the function of the Thin-film Semiconductor in the diagram is generally performed by the "high-resistivity semiconductor film" illustrated in the `737 patent. 22. For thin-film semiconductors made of certain materials, such as undoped

hydrogenated amorphous silicon, an extra doped semiconductor layer (not depicted in the conceptual diagram above) may be added between the thin-film semiconductor and the source and drain electrodes to reduce the series resistance between the channel and the source and drain electrodes. The `737 patent refers to such a doped semiconductor layer as a "low-resistivity semiconductor film," which is distinct from the "high-resistivity semiconductor film" in the `737 patent in which the channel is formed. 23. The physics of a TFT defines certain features or characteristics of each of the

aforementioned layers. For example, the insulating material between the gate electrode and the thin-film semiconductor will serve both to insulate the gate and control the current through the channel region. The current is modulated through a gate capacitance formed by the gate insulating film. The material used to insulate the gate has a "permittivity," which is a parameter that determines the value of the gate capacitance. The total capacitance of the
1912933.2

- 10 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 11 of 40

insulator film will be a function of the composition of material or materials used, as different materials have different permittivity values, and the total thickness of these materials. An engineering decision on the thickness and composition of the material or materials spanning the region between the upper surface of the gate electrode and the bottom surface of the thin-film semiconductor must be made. In general, for a high performance TFT both a high value capacitance is desired (thinner materials or higher permittivity values result in higher capacitance) and an effective insulation of the gate electrode (thicker materials insulate better). 24. Physics also dictates that the material directly above the gate insulator ­ i.e.,

the thin-film semiconductor - will always contain the channel. As noted above, the channel will form in a thin band right above the interface with the insulating film, but does not extend into upper films. C. Fabrication of a TFT 25. As can be seen from the previous diagram, a TFT device is made from a

series of different materials deposited as layers and shaped or patterned into device features. The manufacturing process generally entails the formation of layers from bottom to top. Since a layer is typically deposited over the entire surface, the manufacturing process also generally requires the removal or etching of the layer from certain regions, for example, to expose a portion of the layer underneath or to create desired features having particular geometric shapes. The removal or etching of a layer from certain regions typically requires the use of a "mask," which is made of material that is resistive to a removal or etching technique and generally defines the boundaries of the exposed material to be removed or etched.
1912933.2

- 11 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 12 of 40

26.

During the fabrication process, a device is moved among different tools and

machines in order to deposit, clean, etch, and perform other fabrication steps. Deposition or etching of material may occur in a controlled vacuum chamber in order to allow careful control of the process parameters. This allows the process engineer to closely control the deposition rate of the material, for example, or the rate of etching. Between fabrication steps, it may be necessary to move the substrate containing the partially completed devices from one machine (e.g., a vacuum chamber) to another machine. During this time, a device may be generally exposed to the uncontrolled ambient atmosphere, as opposed to the controlled atmosphere within a vacuum chamber or the like. Since the ambient atmosphere contains oxygen and other potential contaminants or impurities, the exposed surfaces of a device may oxidize or collect undesired contaminants or impurities, thus potentially affecting device performance. V. `737 PATENT 27. The `737 patent describes a particular technique for fabricating a TFT that is

said in the patent to use a reduced number of mask steps. `737 Patent, 1:32-53. Another stated goal of this patent is to fabricate the TFT in a manner that minimizes the "channel series resistance." `737 Patent, 4:9-12. 28. The `737 patent compares its fabrication process to a particular prior art

process. According to the prior art as described in the `737 patent, a gate electrode 2 is formed on an insulating substrate 1, such as a glass substrate:

1912933.2

- 12 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 13 of 40

`737 Patent, 1:12-17. The formation of the gate electrode into the shape of an island is the first masking/etching step described in the prior art sequence. 29. Then, a gate insulating film 3 and an amorphous silicon film 4 are deposited

in sequence, and the latter is etched into the shape of an island as shown in Fig. 1b of the `737 patent:

`737 Patent, 1:17-21. Thus far, the sequence of substrate, gate, insulator, and thin-film semiconductor are the same as shown in the conceptual diagram of a generic TFT depicted earlier. The formation of the thin-film semiconductor into the shape of an island is the second masking/etching step described in the prior art sequence. 30. Next, an insulating film 7 is deposited, and windows are formed for contact

with source and drain regions as shown in Fig. 1c of the `737 patent:

1912933.2

- 13 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 14 of 40

`737 Patent, 1:21-24. The formation of windows in this insulating film is the third masking/etching step described in the prior art sequence. 31. Then, n+ amorphous silicon films 25, 26 and metal (such as Al) films 15, 16

are deposited and selectively etched to form drain and source electrodes 5, 6, thereby resulting in a thin-film transistor as shown in Fig. 1d of the patent below. `737 Patent,1:2529.

(The n+ amorphous silicon films were not depicted in the earlier conceptual TFT diagram but, as noted above, are sometimes added to facilitate the flow of current between the electrodes and the semiconductor.) The complete removal of the center portion of the metal electrode layer and the doped amorphous silicon layer, electrically isolating the source and drain electrodes, is the fourth masking/etching step described in the prior art sequence illustrated in the `737 patent. 32. The'737 patent purports to reduce the number of masking steps over the prior

art depicted in Figs. 1a ­ 1d. The `737 patent technique is illustrated in Figs. 2a ­ 2e, and a very similar alternative process is shown in Figs. 3a ­ 3d. The process starts with the formation of the gate electrode 2 (first masking step) atop an insulating substrate 1 (such as glass, quartz, ceramic, insulator-coated silicon or metal):

1912933.2

- 14 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 15 of 40

`737 Patent, 2:8-14. 33. In a next step, a gate insulating film 3, a high-resistivity film 4, a low-

resistivity film 20 and a conducting film 30 are successively deposited on the gate electrode 2 and substrate 1 in a continuous and uninterrupted manner, without exposing them to an oxidizing atmosphere. `737 Patent, 2:17-23. The result is illustrated in Fig. 2b:

34.

Alternatively, the "conducting film" may take the form of a single layer,

made up solely of low-resistivity semiconductor film 20. In either case, it is important to the `737 patent that the three films ­ that is, the gate insulating film 3, high-resistivity semiconductor film 4, and conducting film 20 & 30 ­ be deposited continuously without exposure to an oxidizing atmosphere, in order to mitigate oxide formation on the interfaces or the collection of impurities and thus avoid an extra electrical resistance between the source and drain and between the channel region. `737 Patent, 1:32-46, 2:17-23. This is achieved by avoiding a masking step between the deposition of the thin-film semiconductor layer and the deposition of the conducting layer, in contrast to the prior art sequence

1912933.2

- 15 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 16 of 40

described above. As explained further below, the continuous deposition of the claimed method allows those layers to be formed without moving the substrate from a deposition chamber to a masking station, thereby exposing it to the ambient atmosphere. 35. To avoid potential confusion, it is worth noting here an inconsistency

between the claim language and the language of the specification with regard to the term "conducting film." The specification refers to the conducting film as distinct form the lowresistivity semiconductor film, and identifies them with different reference numerals. For example, the `737 patent refers to "conducting film 30 and low-resistivity amorphous silicon film 20 shown in Figure 2c." `737 Patent, 2:63-64. The claim language, however, requires that the low-resistivity semiconductor film is "contained" within the "conducting film," requiring the conclusion that both 30 and 20 are in fact the "conducting film" as that term is used in claim 1. There is also an alternative embodiment to Figs. 2a ­ 2e, shown in Figs. 3a ­ 3d, which is said not to use a conducting film, yet it includes a low-resistivity semiconductor film. While the claim language and specification appear to be inconsistent, I will assume for the present that the "conducting film containing a low resistivity semiconductor film" described in claim 1 also pertains to Figs. 3a ­ 3d. 36. Following the successive deposition of the three films, in a following step the

upper films ­ i.e., the conducting film (including low-resistivity semiconductor film 20 if applicable) and high-resistivity amorphous silicon film 4 ­ are etched and left as an island region (second masking step). `737 Patent, 2:54-57. The result is shown in Fig. 2c:

1912933.2

- 16 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 17 of 40

37.

Alternatively, the conducting film may take the form of a single layer made

up solely of low-resistivity semiconductor 20 as illustrated (after shaping into an island region) in the relevant portion of Fig. 3b reproduced below:

`737 FIG. 3b (Partial View) 38. Next, drain and source electrode members 15, 16 are formed on opposite

sides of the island region (third masking step), and the conducting film 30 (including the low-resistivity semiconductor film 20) shown in Fig. 2c are selectively removed with the source and drain electrode members 15, 16 serving as part of the mask to form drain electrode 5 and source electrode 6. `737 Patent, 2:60-66. The result is illustrated in Fig. 2d:

1912933.2

- 17 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 18 of 40

39.

In a final step, as illustrated in Fig. 2e, a surface passivation film 8 is

deposited, and the drain and source electrodes 15, 16 and gate electrode 2 are partly exposed by selective removal of the passivation film 8:

`737 Patent, 3:11-16. 40. Below I will address some of the claim terms that I understand are to be

addressed by the Court, and attempt to provide relevant technical or scientific context as well as opinions as to the meaning of particular claim language to one skilled in the art as of the time the `737 patent was filed in the mid-1980's. I attempt to focus on particular areas where CMO's proposed construction differs from the construction of one of the other parties, and do not necessarily intend to address every aspect of each claim construction, particularly where some part of the term does not appear to be in dispute. 41. Gate insulating film. As noted above, the gate insulating film in the `737

patent is the first of the three films that are "continuously deposited" atop the substrate 1 and gate electrode 2, as shown in Figure 2b of the patent. The gate insulating film is a thickness of insulating material (such as silicon nitride (SiNx), silicon oxide (SiOx), or a multi-layer film made of such materials) with a high electrical resistance, spanning the region from the gate electrode to the high resistivity semiconductor layer, for insulating the gate electrode from the channel that is formed within the region of the high resistivity semiconductor layer that is right above the gate insulating film.
1912933.2

- 18 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 19 of 40

42.

The gate insulating film described in the `737 patent is no different from gate

insulating films as used in the prior art, and as described in my background explanation earlier for TFTs. That is, the gate insulating film lies between the gate electrode and the high-resistivity semiconductor layer that contains the channel, and serves the purpose of insulating the gate electrode from the channel. To perform this function, the gate insulating film must be of adequate thickness. At the same time, the electrical characteristics of the TFT are closely related to the thickness of the gate insulating material above the gate electrode (the thickness above the substrate is not as relevant, as the channel region is directly above the gate electrode). When the TFT is in the "on" state, the insulating layer must yield proper capacitance such that a channel may be formed. Each material that can be used for a gate-insulating film has a material property known as "permittivity." The total capacitance of the gate insulating film will be a function of the permittivity value of material or materials used and the thickness of these materials. As noted previously, an engineering decision must be made based on a balance of the capacitance and insulating properties of the gate insulating film to determine a thickness of gate insulating film that will produce the desired performance for the TFT. All of the material spanning the region from the top of the gate electrode to the high-resistivity semiconductor layer will impact the insulating properties and the capacitance of this film. Therefore, a person of ordinary skill in the art would understand all of this material to constitute the "gate-insulating film." 43. Accordingly, the term "gate insulating film" in the context of the `737 patent

would be understood to mean the entirety of the insulating material that spans the region from the top of the gate electrode to the high-resistivity semiconductor layer.

1912933.2

- 19 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 20 of 40

44.

This view is quite consistent with the description and teachings of the `737

patent. For example, the claimed steps of the method itself, as understood by a person of ordinary skill, require a specific location and dimension for the "gate insulating film." The "first step" of Claim 1 initially requires forming a gate electrode on an insulating substrate. The "second step" begins with depositing the "gate insulating film" followed in immediate succession by the "high-resistivity semiconductor film," therefore bounding the gate insulating film between the gate electrode and the high-resistivity semiconductor film. 45. The parties agree that "continuously depositing" means placing the films

"without intervening films." This necessarily defines the placement of these three films within the TFT device. In particular, according to the specific order of steps recited in claim 1 and taught in the `737 patent, the "gate insulating film" must span the entire region between the "gate electrode" and the "high-resistivity semiconductor film." 46. The dimension of the gate insulating film is also reflected in Figure 2b, which

depicts the gate-insulating film (labeled with the number 3) as spanning the region from the gate electrode (labeled with the number 2) and the high resistivity semiconductor layer (labeled with the number 4).

(annotations added).

1912933.2

- 20 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 21 of 40

As noted previously, the thickness above the substrate depicted to the left and right of the gate is not as relevant, as the channel region is directly above the gate electrode. In those regions to the sides of gate electrode 2, as shown in Fig. 2b, the gate insulating film 3 will generally span from the top of the substrate 1 to the bottom surface of the high-resistivity semiconductor film 4, and would typically be approximately the same thickness as the film above the gate electrode 2 when deposited films such as SiNx or SiOx are used. 47. Furthermore, the `737 patent describes that the "gate insulating film" can be

composed of several layers ("Besides SiNx, a film of SiOx or a multi-layer film made of such materials can be used as said gate insulating film"). `737 Patent, 2:36-38 (emphasis added). Therefore, however many layers may be deposited between the gate electrode and the high-resistivity semiconductor film, a person of ordinary skill would understand them all collectively to be part of the "gate insulating film." 48. In my opinion, CMO's proposed construction therefore provides the proper

meaning of "gate insulating film" in the context of the patent to a person of ordinary skill in the art of thin film transistor manufacture at the time of effective filing date of the `737 patent. 49. CMO's proposed construction also more accurately describes the materials of

the "gate insulating film" and its function. With respect to materials, "SiNx, SiOx, or a multi-layer film made of such materials" is taken directly from the patent specification. `737 Patent, 2:36-38. LGD also proposes that the material be "non-conductive" but this definition is too broad in my view, as it might arguably encompass semi-conductors. A better term would be "insulating material." With respect to function of the "gate-insulating film," CMO proposes "insulating the gate electrode from the channel" while LGD proposes
1912933.2

- 21 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 22 of 40

"insulates the transistor gate from the semiconductor." In my opinion, there is little distinction between these constructions, but the CMO construction is preferable because the purpose is to insulate the gate electrode from the channel which is formed within a region of the high resistivity semiconductor located adjacent to the interface of the gate insulating film when the transistor is active ("ON"). The term "channel" here is preferable, in my view, because several semiconductor layers appear in claim 1, and therefore general reference to "the semiconductor" generically could be confusing. The terms "gate electrode" and "transistor gate" appear to be intended to mean similar things, but "gate electrode" more closely follows the claim language and thus would be preferable in my opinion. 50. High-resistivitity semiconductor film. The "high-resistivity semiconductor

film" is, in the sequence of continuously deposited films, the one that is deposited above the gate insulating film. As explained earlier, in a typical TFT of the type described in the `737 patent, the thin-film semiconductor region between the source and drain acts as the channel. The channel is formed under the influence of the gate voltage and is contained in the region of the high-resistivity semiconductor film adjacent to its bottom surface, i.e., the surface in contact with the gate insulating film. The term "high-resistivity semiconductor film" in the context of `737 claim 1 would therefore be understood by a person of skill in the art to mean a thickness of semiconductor material (such as amorphous silicon or other similar materials) that has a high resistance to current flow and contains the channel formed at the bottom surface of that layer. 51. The term "high-resistivity semiconductor film" in the context of the `737

patent is intimately tied to the function and operation of the channel. As discussed above, a "channel" is an indispensable feature of a thin-film transistor. Moreover, one of the main

1912933.2

- 22 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 23 of 40

goals of the `737 patent is to improve the electrical characteristics of a transistor by reducing "channel series resistance." `737 Patent, 4:9-12. "Channel series resistance" is the total resistance to electric current between the source and drain electrodes that is in series with the TFT channel resistance. The channel series resistance may include, for example, such things as contact resistance, the resistance of the low-resistivity semiconductor film, as well as resistances arising from oxides or other impurities collecting on the interfaces between layers. One alleged difference between the prior art and the process described in the `737 patent is that certain layers, including the channel layer (i.e., high-resistivity semiconductor film), are deposited without exposure to an oxidizing atmosphere. When a layer is exposed to the atmosphere, oxides can be formed or other impurities collected on its surface. `737 Patent, 1:32-40. These can contribute to increased resistance to flow of electrons between the layer below and the layer above. The `737 patent's intended benefit of reduced exposure to an oxidizing atmosphere, therefore, is to lower channel series resistance. 52. The "high resistivity film" in Claim 1 must act as the channel. The physics

of this type of thin film transistor dictates that the layer that interfaces with the gate insulator will always contain the channel. In the `737 patent, the high resistivity film is "continuously deposited" over the gate insulator (i.e., the "gate-insulating film"). Therefore, it must necessarily act as the channel in this type of device. 53. The depiction of the TFT in the preferred embodiment of the `737 patent

supports this conclusion. It states that "the channel areas of the thin-film transistor are safe from damage by cleaning as they are covered with conducting film 30." Col. 3:2-4. As noted above, the term "conducting film," in the claim, includes both the "conducting film" and the "low resistivity film 20," and from the context, that appears to be how the term is

1912933.2

- 23 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 24 of 40

used here. The layer covered by the conducting film is the high-resistivity semiconductor film. 54. Besides the points discussed above, CMO's construction also correctly

specifies that the "high-resistivity film" must in fact have high resistance, not just "higher" resistance than some other layer. If the "high resistivity film" was in fact a material with low resistance that just happened to be marginally higher than the "low resistivity film," the TFT would not work as intended. For example, the TFT would have high leakage current, meaning that current could flow between the source and drain even without voltage applied from the gate. The resistivity of the "high-resistivity film" must be high enough for the transistor to work as intended, not simply higher than that of the low-resistivity film. 55. Without exposing ... to an oxidizing atmosphere. The `737 patent requires

that the gate insulating film, high-resistivity semiconductor film, and conducting film must be deposited "without exposing them to an oxidizing atmosphere." This means that these films must be deposited without permitting them to come into contact with an uncontrolled ambient atmosphere which contains oxidizing agents. 56. As described earlier, the manufacturing process of TFTs include the use of

various deposition chambers in order to deposit films, as well as other tools. These deposition chambers are usually a controlled environment where gases are injected and combined, and the resulting reactions cause layers to be deposited on a surface (the substrate or a previous layer). The manufacturing process also includes other steps, such as cleaning, masking, etching, and so forth. Typically, in the manufacturing processes in use at the time the `737 patent was filed, when samples were moved from one station (such as a deposition chamber) to another (such as a lithography tool for masking), they would be exposed to an
1912933.2

- 24 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 25 of 40

ambient atmosphere. Oxygen and its compounds (such as water vapor) found in the ambient atmosphere can cause undesirable oxidation of certain materials. The sample could also be exposed to other undesirable impurities, particles or other contaminants in the ambient atmosphere. The manufacturing process must therefore be carefully planned so that samples would be moved between stations at times that minimize undesirable exposure to the uncontrolled atmosphere (for example, when none of the exposed surface is particularly sensitive to oxidation and other contaminants). 57. The alleged innovation of the `737 patent is a process of depositing layers of

a TFT that minimizes the oxidation or collection of contaminants or impurities at the interfaces between the gate-insulating film, high-resistivity semiconducting film, and lowresistivity semiconducting film. In describing the prior art, the specification states "since the masking step precedes the deposition of n+ amorphous films 25, 26, natural oxide is produced on the exposed surface of amorphous silicon film 4. Although such natural oxide can be removed... the possibility is still great that oxygen and its compounds as well as other impurities can collect on the laminate surface as it is exposed to the atmosphere." `737 col. 1:33-40. A person of ordinary skill in the art would have understood that "the atmosphere" in this context refers to the uncontrolled ambient atmosphere that will be encountered in an ordinary manufacturing process when a sample is moved between the lithography tool for "the masking step" and the chamber used for the "deposition of n+ amorphous films." Between these two process steps, exposing the sample to the ambient atmosphere, which contains oxygen and its compounds (like water vapor) as well as other possible contaminants, could lead to formation of oxides or collection of other impurities on the laminate surface of the sample.

1912933.2

- 25 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 26 of 40

58.

As an alternative and alleged improvement to the prior art technique

described above, the patent describes the "continuous deposition" of the gate insulating film, high-resistivity semiconductor film and conducting film, without a masking or other operation between these deposition steps. The patent requires that this "continuous deposition" of these layers take place "without exposing them to an oxidizing atmosphere." Based on the patent's comparison of the claimed process with the prior art of Figs. 1a ­ 1d, a person of skill would also have understood that the claimed step of avoiding exposure to an oxidizing atmosphere refers to the uncontrolled ambient atmosphere that would be encountered between the deposition chamber and another station, such as a lithography tool or cleaning tool. The description at column 2, lines 17-53 of the `737 patent relating to this part of the fabrication process indicates that all of the relevant films would be deposited using the same tool (either in the same chamber or "in-line" chambers adjacent to each other within the same tool ­ see 2:30-36), thus avoiding the need to transfer the partially completed sample between different tools, which would expose it to the outside ambient atmosphere including its oxidizing agents and contaminants. 59. This point is emphasized again at column 2, lines 33-36 of the `737 patent,

which states in connection with successive deposition of the relevant films: "Further, when a sputtering or metalizing chamber is additionally provided, conducting film 30 can also be deposited continuously without exposure to the atmosphere." The `737 patent explains here that the addition of another (e.g., in-line) chamber in the depositing station avoids the need to transfer the sample between tools, which would expose it to "the atmosphere" (that is, the outside ambient atmosphere). In other words, the `737 patent equates "an oxidizing atmosphere" with "the atmosphere" (i.e, the ambient atmosphere), and tends to use these terms in an interchangeable fashion.
1912933.2

- 26 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 27 of 40

60.

The fact that those skilled in the art would understand reference to "the

atmosphere" in the `737 patent to mean the outside or uncontrolled ambient atmosphere is further reflected by contemporaneous U.S. Patent No. 4,343,081 (the `081 patent, Exhibit E hereto) issued in August 1982 to Francois Morin et al. That patent is directed to essentially the same problem as the `737 patent, including making a thin film transistor (TFT) by successively depositing various films (semiconductor, insulator and metal) while avoiding contamination (or "pollution") at the relevant interface(s). See `081 Patent at col. 1:29-33, 2:4-9. The '081 patent explains that such contamination can be avoided by forming all of the layers "in vacuo" (that is, in conditions of a vacuum chamber) and "in one manufacturing cycle." Id., 1:29-33, 2:4-9. In other words, the various films are formed "successively" and "without contact with the outside atmosphere." Id., 2:33-40, Abstract. The `081 patent uses the terminology "outside atmosphere" (that is, the uncontrolled ambient atmosphere) to refer to what the `737 patent refers to simply as "the atmosphere," but in both cases they mean the same thing: the films should be successively deposited using the same tool while preventing contact with the uncontrolled ambient atmosphere. 61. Therefore, in my opinion, CMO's proposed construction provides the proper

meaning of "without exposing them to an oxidizing atmosphere" in the context of the `737 patent to a person of ordinary skill in the art of thin film transistor manufacture at the time of effective filing date of the `737 patent. 62. The alternative construction offered by LGD, which focuses on the outcome

rather than the process itself, is vague in my view. The LGD proposal requires that the result is an interface without a "detectable amount of oxidation." First, the term "detectable" is not easily applied because it would be highly dependent on the detection

1912933.2

- 27 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 28 of 40

technology used. There are technologies available that can detect extremely small amounts of oxidation. XPS (x-ray photoelectron spectroscopy), TEM (transmission electron microscopy), SEM (scanning electron microscopy) and other techniques can be applied to detect minute amounts of oxides in structures. In addition, remarkable advances in characterization techniques are continually being realized at the nano- and the atomic scales. It is unclear which of these techniques would be applicable when determining whether an oxide is "detectable." Also, the LGD proposal focuses only on oxide detection, whereas `737 patent is concerned about other impurities from the atmosphere. See `737 patent 1:3540 ("Although such natural oxide can be removed by an aqueous solution of hydrofluoric acid (HF) or a similar substance, the possibility is still great that oxygen and its compounds as well as other impurities can collect on the laminate surface as it is exposed to the atmosphere."). In fact, the above quoted text suggests that because there was already a known solution in the prior art for dealing with oxide formation, if anything the `737 patent was possibly more concerned about other impurities or contaminants forming on the interfaces, but these concerns are absent from LGD's proposed construction. 63. Selectively removing said conducting film exposed on said island region.

After the various films discussed earlier are "continuously deposited," the process described in Claim 1 requires etching the semiconductor film and conducting film into an "island region", adding a source and drain electrode on either side of the island region, and then "selectively removing said conducting film exposed on said island region." This would be understood by one skilled in the art to mean the act of eliminating all the exposed conducting film in the space between the edges of the source and drain electrodes.

1912933.2

- 28 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 29 of 40

64.

When those skilled in the art of semiconductor processing refer to

"removing" a layer or film, what is meant is removing the entirety of the layer or film that is exposed to the removal process. This is how the term "removal" would be understood in the context of the `737 patent. 65. This understanding is also reflected in the `737 patent text and illustrations,

which shows the entirety of the conducting film exposed between the source and drain electrodes as being "removed." This process is shown graphically, for example, in the sequence of steps in Figures 2c and 2d of the `737 patent. (An analogous process is also depicted in the sequence of `737 Figs. 3b and 3c). For clarity of illustration, I have added below a figure to the series of figures in the patent, which I have designated figure 2d' representing the acts described in the specification but not illustrated. To repeat my earlier explanation, Figure 2c is the result of etching the top layers of the TFT, leaving an "island" consisting of the conducting film 30, the low-resistivity amorphous silicon film 20 and the high-resistivity amorphous silicon film 4. 2:54, 57. The next step, described but not depicted, is that drain and source electrodes are added over each end of the island region. 2:60-62. This step is depicted below in Fig. 2d' (modified). Finally, "conducting film 30 and low-resistivity amorphous silicon film 20 are selectively removed," as depicted in figure 2d. As can be seen from the figure, all of the conducting film in the space between the edges of the source and drain electrodes is removed.

1912933.2

- 29 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 30 of 40

66.

It is particularly important that the conducting layers (depicted here as 20 and

30) are fully removed. If a small amount of layer 20 remains, there would be a risk that the TFT would be subject to shorting and not work properly. In fact, the `737 patent recommends over-etching to ensure complete removal of the conducting film and avoid this type of failure. `737 Patent, 3:7-10. This confirms my view that the `737 patent intended "selectively removing" the exposed film to mean eliminating all of the exposed film.
1912933.2

- 30 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 31 of 40

67.

The context of the claim also supports this construction. The claim requires

that the source and drain electrodes serve as at least part of the mask for this removal step. A mask is made of material that is resistive to a removal technique and defines by its edges the boundaries of the exposed material selected for removal. Therefore, since the source and drain electrodes are serving as a part of the mask in connection with the selective removal step, the profile of the exposed material removed must match the positions of the source and drain electrodes, as depicted in figure 2d. 68. In my opinion, CMO's proposed construction provides the proper meaning of

"selectively removing said conducting film exposed on said island region" in the context of the `737 patent to a person of ordinary skill in the art. VI. THE `449 PATENT 69. The `449 patent describes a technique for forming a wire structure for an

LCD array. As described earlier, a TFT can be used as an "on/off switch" for controlling the state of a pixel on an LCD display. Each TFT needs to be electrically connected to external components in order to operate. These external components supply electrical signals which eventually interact with the source and the gate electrodes. The signals are brought to the pixel by metal lines. Lines that supply the signal to the source electrodes are known as Data Lines, and lines supply the signal to the gate electrode are called Gate Lines. The electrodes of the TFT and the metal lines are often times not electrically connected until the later steps in the manufacturing process. Often times these conducting structures are separated laterally and/or vertically by one or more insulating layers. In order to electrically connect these structures, small openings are etched completely through the insulating material to expose the conductive layers beneath. These openings are sometimes referred to as contact holes or
1912933.2

- 31 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 32 of 40

vias. After these openings are created, conductive material is deposited to fill the contact holes or vias and form parts of the wiring structures necessary to electrically connect the conductive layers beneath the insulating material. 70. An example of a process in which contact holes are used to expose

underlying conductive layers so that they can be electrically connected by additional conductive material is illustrated in Figs. 1a ­ 1e of the `449 patent (by contrast, Fig. 3 only shows the end result of such a process). The process of Figs. 1a ­ 1e is said in the `449 patent to be Prior Art. First, Figure 1a illustrates the deposit of a conductive layer on a transparent glass substrate 1, followed by patterning to form features such as a source pad 2A, gate electrode 2, storage capacitor 20 and a gate pad 2B (`449 Patent, 1:34-39):

71.

Next, as shown in Fig. 1b, a gate insulating film is formed over the entire

surface of the substrate, followed by the formation of an island of amorphous silicon 4 and a doped semiconductor layer 5 over the gate electrode 2 (`449 Patent, 1:40-50):

1912933.2

- 32 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 33 of 40

72.

Then, as shown in Fig. 1c, the gate insulating film 3 is selectively etched to

expose the source pad 2A and gate pad 2B, in order to enable communicate information from an external driving circuit to the gate and source (`449 Patent, 1:52-55). The selective etching results in contact holes exposing the source pad 2A and gate pad 2B:

73.

Next, as shown in Fig. 1d, a transparent conductive layer such as Indium Tin

Oxide (ITO) is deposited on the entire surface and patterned to form, among other things, patterns 6A on the source pad 2A and gate pad 2B, respectively (`449 Patent, 1:56-60, although the patent text erroneously refers to "6B" above the gate pad, suggesting that the label in the figure over 2B should actually be "6B")):

74.

As shown next in Fig. 1e, the TFT is formed on the active layer and includes

a conductive layer deposited on the substrate and simultaneously patterned to form source and drain electrodes 7 and 8, respectively. `449 Patent, 1:61-64. As can be seen in Fig. 1e,
1912933.2

- 33 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 34 of 40

the source electrode is connected to source pad 2A through one contact hole, and the drain electrode 8 is in contact with impurity-doped semiconductor layer 5 and pixel electrode 6:

75.

The cross-sectional views illustrated in Figures 1a ­ 1f, 2a ­ 2d and 3 of the

`449 patent are slightly broader in scope than the cross-sectional views shown in the `737 ­ in addition to the transistor (TFT), they also include other features such as the storage capacitor, source pad, and gate pad. The capacitor, as discussed before, maintains the voltage at the pixel electrode. The source pad and gate pads connect the transistor to the circuit that drives and controls the display. I have labeled the different general portions of Figure 3 of the `449 patent below for illustration purposes, with the caveat that there is not necessarily a precise dividing point between the regions identified below, at least not as can be identified at this level of illustration.

1912933.2

- 34 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 35 of 40

Source Pad

TFT

Capacitor

Gate Pad

76.

In the following section I will address some of the claim disputes that I

understand may be presented to the Court and, as with the `737 Patent, attempt to provide relevant technical or scientific context as well as opinions as to the meaning of particular claim language to one skilled in the art as of the time the `449 patent was filed in the mid1990's. As before, I do not necessarily intend to address every aspect of each claim construction, but attempt to focus more on particular areas where CMO's proposed construction differs from the construction of one of the other parties. 77. Conductive layer. Claim 1 describes a wiring structure with a first

"conductive layer" and a second "conductive layer." In the context of the `449 patent, the term "conductive layer" would be understood by one skilled in the art to mean a single thickness of electrically conductive material that may include one or more patterned features, all of the same uniform material (i.e., single material). 78. In the art of semiconductor manufacture, intended structures are created by

initially depositing a layer material that blanket the entire surface, followed by steps to remove the undesired material. The patterns of material left on the surface are the remnants of the initial layer that was deposited. These patterns would naturally share common
1912933.2

- 35 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 36 of 40

material characteristics. In other words, structures that were formed from a common deposition step and subsequent patterning can be thought of as belonging to a common "layer." The simultaneous formation of the patterns/structures is intended to minimize the cost and time in the manufacture of the final product. Therefore "conductive layer" would mean the initial conducting material (such as metals and certain types of oxides, such as indium tin oxide for example) that is deposited according to a given process, as well as the resulting pattern of conducting material after subsequent patterning. 79. This meaning of "conductive layer" is confirmed by the `449 patent

specification. With regard to the conductive layer including one or more patterned feature, the `449 specification states, for example, that "a conductive layer is formed on a transparent glass substrate 1 and patterned to form a gate electrode 2, a storage capacitor electrode 2D, and a gate pad 2C, all of the same material." `449 patent at 3:44-47. The specification repeatedly speaks of the "conductive layer" as including various patterned features, as is captured by the language proposed in CMO's construction. `449 Patent, 1:34-37, 1:56-60, 1:61-64, 2:37-46, 3:44-47, 4:64 - 5:1, 5:6-8, 5:16-22. Another example is in the Summary of the Invention, which describes that a "gate electrode[,] a gate pad and a source pad [are] formed on the substrate as a first conductive layer." `449 Patent, 2:37-40.1 Along these same lines, claim 10 of the '449 Patent also illustrates that a conductive layer may include multiple patterned features ­ specifically, "a gate electrode, a gate pad, and a source pad." `449 Patent, 7:36-39.

While the `449 patent text in the summary erroneously has a semicolon following "gate electrode" instead of a comma, it is clear that the gate electrode is part of the first conductive layer because of the later description appearing in the detailed description of the embodiments as well as claim 10. See, e.g., `449 Patent, 4:50-52.
1912933.2

1

- 36 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 37 of 40

80.

The `449 specification also explains that, since all of the patterned features of

a conductive layer are initially deposited at the same time, before patterning, all of the patterned feature are "of the same material" (`449 Patent, 3:44-47), and this is an inherent characteristic of the patterned features given that they are all deposited at the same time, as part of the same process. The `449 patent repeatedly confirms the fact that the patterned features of the conductive layer are all the same material. For example, it states that "source pad 2A is composed of gate material, as in the conventional method, and is formed at the same time as gate 2, storage capacitor electrode 2D and gate pad 2B" (`449 Patent, 4:50-53), and again that "both the first (45) and fourth (60) contact holes are formed over the source pad 2A (formed of the same material as the gate) and source electrode, respectively...." `449 Patent, 4:56-59. Likewise, a transparent conductive layer of indium tin oxide (ITO) is deposited and patterned into various features, all of the same uniform material ­ ITO. See `449 Patent, 1:56-60, 5:16-22. There is no instance in which the `449 patent describes a conductive layer patterned into features having different materials, and, again, since the conductive material is deposited uniformly over the substrate the patterned features formed from that layer will always share the same uniform composition. 81. In my opinion, CMO's proposed construction provides the proper meaning of

"conducting layer" in the context of the patent to a person of ordinary skill in the art of thin film transistor manufacture at the time of effective filing date of the `449 patent.

1912933.2

- 37 -

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 38 of 40

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 39 of 40

Case 1:06-cv-00726-JJF

Document 388

Filed 08/12/2008

Page 40 of 40

Case 1:06-cv-00726-JJF

Document 388-2

Filed 08/12/2008

Page 1 of 15

EXHIBIT A

0.0 01

Case 1:06-cv-00726-JJF

Document 388-2

Filed 08/12/2008

Page 2 of 15
1

VITA MILTIADIS K. HATALIS
. PERSONAL 1959, Thessaloniki, Greece Married (3 children) USA

Year and place of birth: Marital status: Citizenship: . EDUCATION

Doctor of Philosophy (Ph.D.)

Electrical and Computer Engineering, 1987 Carnegie Mellon University, Pittsburgh, PA USA Electrical and Computer Engineering, 1984 State University of New York at Buffalo, NY, USA Physics 1982 Aristotle University of Thessaloniki, Greece

Master of Science (M.S.)

Batchelor of Science (B.S.) . EMPLOYMENT

Academia 1995-today Professor Lehigh University, Bethlehem, PA Department Electrical & Computer Engineering Lehigh University, Bethlehem, PA Department Electrical & Computer Engineering Lehigh University, Bethlehem, PA Department Electrical & Computer Engineering Carnegie Mellon University; Pittsburgh, PA Department Electrical & Computer Engineering State University of New York at Buffalo, NY Department Electrical & Computer Engineering Display Research Laboratory Lehigh University Microelectronics Research Laboratory Lehigh University

1991-1995 Associate Professor

1987-1991 Assistant Professor

1984-1987 Research Assistant

1982-1984 Teaching Assistant ------------------------1993-today Director

1988-1993 Associate Director --------------------------Industry 1987-today Consultant

IBM, Kodak, Litton, Corning, Spire, Sharp, eMagin, Sterling Diagnostics, Diamonex Dow Corning, Intevac, etc XEROX Palo Alto Research Laboratory

1992

Visiting Scientist

Exhibit A, Page 39

Case 1:06-cv-00726-JJF

Document 388-2

Filed 08/12/2008

Page 3 of 15
2

IV.

TEACHING RECORD · Microelectronics Technology · Fundamentals of Semiconductor Devices · Semiconductor Materials and Device Characterization · Thin Film Materials and Devices · Introduction to VLSI Design EDITOR "Flat Panel Display Materials II" Materials Research Society Symposium Proceedings vol. 424 Published by the Materials Research Society, 1997 "Proceedings of the Second International Workshop on Active Matrix Liquid Crystal Displays" Published by the IEEE Society, 1996

V.

VI. SUPERVISION OF STUDENTS Ph.D. Dissertations: 1. F. Lin (1994) "Structural and Electrical Characteristics of Polycrystalline Semiconductors for Thin Film Transistor Applications" 2. A. Voutsas (1994) "Low Temperature Deposition of Polycrystalline Silicon for Active Matrix Liquid Crystal Applications" 3. K. Olasupo (1994) "Physics and Technology of Submicron Polysilicon Thin Film Transistors." 4. J. Kung (1994) "Effect of Gate Dielectric on Performance of Polysilicon Thin Film Transistors" 5. G. Sarcona (1995) "Effects of Silicides and Device Structure on the Characteristics and Circuit Performance of Polysilicon Thin Film Transistors for Active Matrix Liquid Crystal Display" 6. S. H. Lin (1995) "Physics, Technology and Characterization of Polysilicon Thin Film Transistors with Low Leakage Current Performance." 7. M. Stewart (1999) "Polysilicon Devices for Large Area Electronics Applications: Organic Light Emitting Diode Displays and X-Ray Sensors." 8. R. Howell (2000) "Advanced Metallization and Applications to Large Area Active Matrix Arrays and Polysilicon Thin Film Transistors" 9. F. Nkansah (2001) "Technology and Reliability of Sub-Micron 1T-Flash Electrically Erasable Progr