Free Claim Construction Opening Brief - District Court of Delaware - Delaware

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IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF DELAWARE TRANSMETA CORPORATION, Plaintiff, ) ) ) ) ) ) ) ) ) )

v. INTEL CORPORATION, Defendant.

C.A. No. 06-633 (GMS)

TRANSMETA CORPORATION'S OPENING CLAIM CONSTRUCTION BRIEF MORRIS, NICHOLS, ARSHT & TUNNELL LLP Jack B. Blumenfeld (#1014) Karen Jacobs Louden (#2881) Richard J. Bauer (#4828) [email protected] 1201 N. Market Street Wilmington, DE 19899 (302) 658-9200 Attorneys for Plaintiff Transmeta Corporation

OF COUNSEL: Robert C. Morgan ROPES & GRAY LLP 1211 Avenue of the Americas New York, NY 10036-8704 (212) 596-9000 Norman H. Beamer Sasha G. Rao Gabrielle Higgins ROPES & GRAY LLP 525 University Avenue Palo Alto, CA 94301 (650) 617-4000 John O'Hara Horsley TRANSMETA CORPORATION 3990 Freedom Circle Santa Clara, CA 95054 October 19, 2007

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TABLE OF CONTENTS I. II. III. NATURE AND STAGE OF THE PROCEEDINGS..........................................................1 SUMMARY OF THE ARGUMENT..................................................................................1 STATEMENT OF FACTS..................................................................................................1 A. B. IV. The Transmeta Patents...............................................................................................1 The Intel Patents ........................................................................................................2

THE PROPER CONSTRUCTION OF THE DISPUTED TERMS....................................2 A. The `061 Patent..........................................................................................................2 1. 2. 3. 4. 5. 6. 7. "determining a maximum allowable power consumption level..."..................3 "determining a frequency and a voltage" / "determining a voltage-frequency pair"....................................................................................4 "clock frequency generator" ............................................................................4 "means for detecting. . . and causing"..............................................................5 "a state of said computer processor"................................................................6 "said computer processor determining a frequency and a voltage" / "a computer processor determining a voltage-frequency pair".......6 "operating conditions of the central processor" / "operating conditions internal to said computer processor" / "internal conditions of a computer processor".........................................................................................................8 "central processing unit" / "processor" ..........................................................11 "first registers each for holding the integer data" and "second registers each for holding the integer data and for holding floating point data" ..........12 "a field" . . . "specifying which of the first and second register sets is to be accessed" ...........................................................................................14 "reading means . . ." and "writing means . . ."...............................................16 "read access means" and "write access means".............................................20 Boolean Execution Unit Terms......................................................................22 "register renaming" ........................................................................................26

B.

The Multiple Typed Register Patents ........................................................................9 1. 2. 3. 4. 5. 6.

C.

The Register Renaming Patents...............................................................................23 1.

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2.

"associating said index-addressable temporary storage location assigned to said previous instruction with said input" / "to associate said temporary storage location assigned to said previous instruction with said input" ..............................................................................................28 "computer system" / "processor" ...................................................................29 "instruction window" .....................................................................................30 "data dependency checker" ............................................................................32 "one of a plurality of storage locations being determined by a location of said instruction in an instruction window" / "storage locations determined by the location of an instruction in an instruction window" .......33 "means for passing" .......................................................................................34 "tag assignment means" .................................................................................35 `526 method claims 1, 2 and 34: no order of steps required .........................37 Basic Memory Addressing Terms..................................................................39 "Fast/Tentative/Speculative Addressing," And Related Terms .....................44 Memory And Storage Terms..........................................................................48 The `375 Patent ..............................................................................................49 The Address Translation Patents....................................................................53 The Pack/Unpack Patents , Multiply-Add Patent and Intra-Add Patent........55

3. 4. 5. 6.

7. 8. 9. D. 1. 2. 3. E. 1. 2. 3. V.

The Speculative Address Translation Patents..........................................................37

The Intel Patents ......................................................................................................49

CONCLUSION .................................................................................................................60

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TABLE OF AUTHORITIES Altirus, Inc. v. Symantec Corp., 318 F.3d 1363 (Fed. Cir. 2003)......................................37 Comark Communs., Inc. v. Harris Corp., 156 F.3d 11826 (Fed. Cir. 1998) ....................12 Intervet Am. v. Kee-Vet Labs., 887 F.2d 1050 (Fed. Cir. 1989)..........................................7 Micro Chem., Inc. v. Great Plains Chem. Co., 194 F.3d 1250 (Fed. Cir. 1999) ..................................................................18, 19, 35 Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005).....................................................4 Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298 (Fed. Cir. 1999) .................44

STATUTES 35 U.S.C. §112, ¶6 ..........................................................................6, 17, 18, 19, 35, 36, 54

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TABLE OF ABBREVIATIONS

The abbreviations in this memorandum use the following format:

"A__" "B__" "D__" "A__, 1:2-4" "Term __" `061 patent `687 patent `986 patent `449 patent `624 patent `526 patent `433 patent `503 patent `733 patent `668 patent `669 patent `375 patent `554 patent `605 patent `101 patent `275 patent `634 patent `529 patent

JA-A page numbers in the Joint Appendix for the Transmeta patents JA-B page numbers in the Joint Appendix for the Transmeta patents JA-D page numbers in the Joint Appendix for the Intel patents Page number in the Joint Appendix, followed by patent column and line numbers The claim terms as numbered in the Joint Claim Construction Chart, D.I. 92 Transmeta U.S. Patent No. 7,100,061 (A1-13) Transmeta U.S. Patent No. 5,493,687 (A14-33) Transmeta U.S. Patent No. 5,838,986 (A34-55) Transmeta U.S. Patent No. 6,044,449 (A56-76) Transmeta U.S. Patent No. 5,737,624 (A77-97) Transmeta U.S. Patent No. 5,974,526 (98-119) Transmeta U.S. Patent No. 6,289,433 (A120-41) Transmeta U.S. Patent No. 5,895,503 (A142-57) Transmeta U.S. Patent No. 6,226,733 (A158-74) Transmeta U.S. Patent No. 6,430,668 (A175-88) Transmeta U.S. Patent No. 6,813,699 (A189-201) Intel U.S. Patent No. 5,745,375 (D1-10) Intel U.S. Patent No. 5,617,554 (D11-34) Intel U.S. Patent No. 5,802,605 (D35-57) Intel U.S. Patent No. 5,819,101 (D58-86) Intel U.S. Patent No. 5,881,275 (D87-114) Intel U.S. Patent No. 6,385,634 (D115-35) Intel U.S. Patent No. 6,418,529 (D136-58)

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I.

NATURE AND STAGE OF THE PROCEEDINGS Transmeta Corp. ("Transmeta") filed this action on October 11, 2006, asserting that Intel

Corporation ("Intel") infringes eleven Transmeta patents. Intel has asserted counterclaims, including claims that Transmeta infringes seven Intel patents. Pursuant to the Court's Scheduling Order (D.I. 25), fact discovery is set to close on February 1, 2008. Expert discovery closes on May 9, 2008. A pretrial conference is scheduled for November 3, 2008 and trial is set to begin on December 1, 2008. The parties filed their Joint Claim Construction Chart on October 10, 2007 (D.I. 92). This is Transmeta's opening claim construction brief directed to both the Transmeta and Intel patents. II. SUMMARY OF THE ARGUMENT Transmeta's approach to claim construction is consistent. Whether raising potential terms for construction in Transmeta's patents or proposing a construction for terms in Intel's patents, Transmeta bases its construction on the claim language and the intrinsic evidence. Intel's approach to claim construction is self-servingly inconsistent. When construing its own patents, Intel believes that few terms need construction, and those that are construed are calculated to seek infringement where there is none, or to avoid invalidity. For example, in construing the term "processor" in its own patent, Intel says that no construction is required. Intel asserts that when construing Transmeta's patents, the word "processor" should be limited to only a processor using a specific type of instruction set. III. STATEMENT OF FACTS A. The Transmeta Patents

The eleven Transmeta patents in suit are in four separate "families" of patents. The first family consists of one patent, U.S. Patent No. 7,100,061 ("the `061 patent"), and relates to adaptive power control. The "Multiple Typed Register" patents consist of U.S. Patents Nos.

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5,493,687; 5,838,986 and 6,044,449. The "Register Renaming" patents consist of U.S. Patents Nos. 5,737,624; 5,974,526 and 6,289,433. The "Speculative Address Translation" patents consist of U.S. Patents Nos. 5,895,503; 6,226,733; 6,430,668 and 6,813,699. An overview of each Transmeta patent family is included in the discussion of the proper construction of the disputed terms below. B. The Intel Patents

The seven Intel patents in suit are in five separate "families" of patents. The first family consists of one patent, U.S. Patent No. 5,745,375 (the "Power Usage" patent). The "Address Translation" patents consist of U.S. Patent Nos. 5,617,554 and 5,802,605. The "Pack/Unpack" patents consist of U.S. Patent Nos. 5,881,275 and 5,819,101. The fourth and fifth families each consist of one patent: U.S. Patent No. 6,385,634 (the "Multiply-Add" patent) and U.S. Patent No. 6,418,529 (the "Intra-Add" patent). An overview of each Intel patent family is included in the discussion of the proper construction of the disputed terms below. IV. THE PROPER CONSTRUCTION OF THE DISPUTED TERMS A. The `061 Patent

The `061 patent in suit, entitled "Adaptive Power Control," describes methods and apparatus for controlling the power consumed by a processor. Software monitors the operating characteristics of the processor. The monitored conditions may include, for example, present frequency and voltage of operation, temperature of operation, or the amount of time that the processor spends in one or more idle states (e.g., halt or sleep). The processor's power consumption is a function of the operating voltage and frequency of the processor. Based on its monitored conditions or operating characteristics, the processor determines an appropriate frequency and appropriate voltage of operation and changes the power consumption by changing the frequency and voltage of operation to the determined values. In this manner, the processor

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can reduce power consumption, thereby increasing the operating battery life of portable computers or similar devices. To further increase the efficiency of the processor, the processor continues to execute instructions while changing the voltage. 1. "determining a maximum allowable power consumption level..." Proposed Constructions Transmeta - based on an operating condition of the processor, the computer processor determines a maximum allowable power consumption level by determining a corresponding maximum frequency and a minimum voltage which allows operation at the maximum frequency. Intel - after determining a maximum allowable power consumption level from an operating condition of the processor, the computer processor determines, in a separate step, a maximum frequency which provides power not greater than the determined allowable power consumption level, and the computer processor determines, in another separate step, a minimum voltage which allows operation at the determined maximum frequency.

Claim Language determining a maximum allowable power consumption level from an operating condition of the processor, said computer processor determining a maximum frequency which provides power not greater than the allowable power consumption level, said computer processor determining a minimum voltage which allows operation at the maximum frequency determined (claim 1)

Transmeta's proposed construction is supported by the claim language itself, which states that the maximum allowable power consumption level is determined by "determining a maximum frequency which provides power not greater than the allowable power consumption level... [and a] minimum voltage which allows operation at the maximum frequency determined." (A10, claim 1). It also is consistent with the specification, which discloses that power usage is determined by the voltage and the frequency expressed in equation form as P=CV2f (A7, 1:42-56), as well as with the description of the preferred embodiment (A4, Fig. 2; A9, 5:15-67). Intel's proposed construction is contrary to the claim language and separates determining a maximum allowable power consumption level from the very steps which make that determination. It would create separate steps, when they are not separate, and would read the preferred embodiment out of the claim.

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2.

"determining a frequency and a voltage" / "determining a voltagefrequency pair" Proposed Constructions Transmeta - No construction necessary ­ plain and ordinary meaning. Intel - determine a frequency and a voltage based at least on analyzing commands to be executed by the processor.

Claim Language "determining a . . . frequency. . . [and a] voltage" (claim 1) "determining a frequency and a voltage" (claims 15, 23, 30) "determining a voltage-frequency pair" (claim 39)

These are well understood terms that do not need construction. Phillips v. AWH Corp., 415 F.3d 1303, 1314 (Fed. Cir. 2005). Intel does not actually construe these terms, but improperly seeks to add the limitation "based at least on analyzing commands to be executed by the processor." Intel appears to be adding this limitation based on its position that the specification never discloses increasing the frequency and voltage of operation without "analyzing commands to be executed by the processor." This ignores Figure 2, which shows that the control software monitors operating conditions (such as present frequency and voltage of operation, temperature of operation, or the amount of time that the processor spends in one or more idle states), without any analysis of commands to be executed, and determines whether those conditions indicate that the frequency and voltage of operation should be changed, and then increases or decreases the frequency and voltage accordingly. Intel's attempt to narrow the claim language to exclude the Figure 2 embodiment should be rejected. 3. "clock frequency generator" Proposed Constructions Transmeta - No construction necessary ­ plain and ordinary meaning. Intel - a unit that provides individual clock frequencies for each of a plurality of components including a processing unit of the processor, the system memory, and the system bus.

Claim Language "clock frequency generator" (claims 8, 56)

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This term requires no construction, and should be given its plain and ordinary meaning. Intel's proposed construction would insert the limitations that the clock frequency generator "provide individual clock frequencies for each of a plurality of components including a processing unit of the processor, the system memory, and the system bus." Moreover, the doctrine of claim differentiation prevents the term "clock frequency generator" from being construed to require these limitations in claim 56. Claim 58 depends from claim 56 and explicitly provides that the clock frequency generator "is further operable to concurrently generate frequencies for a plurality of functional units of the computing device." (A12-13). To define clock frequency generator as proposed by Intel would impermissibly eliminate any distinction between claims 56 and 58 of the `061 patent. Claim 8 states that the clock frequency generator provides "one of a plurality of selectable output clock frequencies to the processing unit." (A10). Accordingly, the claim itself specifies what the clock frequency generator provides, and it is not what Intel would add to the clock frequency generator element. 4. "means for detecting. . . and causing" Proposed Constructions Transmeta - The structure is control software and a set of registers in the processor ­ such as the clock divider register 22 ­ in which are stored a multiplier and dividers computed by the processor (or determined via table lookup) based on operating conditions of the processor. Intel - The structure is control software executing on the processor and the cooperating hardware on the processor.

Claim Language means for detecting the values indicative of operating conditions of the central processor and causing the power supply and clock frequency generator to furnish an output clock frequency and voltage level for the central processor and to generate concurrently frequencies which are selected for optimum operation of a plurality of functional units of the computing device (claim 8)

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The parties agree that this claim element is a means-plus-function limitation that must be construed according to 35 U.S.C. § 112, ¶ 6, and that the claimed function is as recited. They disagree as to the structure that corresponds to the specified function. The specification discloses that the structure used for performing the specified function is control software and a set of registers in the processor ­ such as the clock divider register 22 ­ in which a multiplier and dividers computed by the processor (or determined via table lookup) are stored. (A3, Fig. 1, master control unit 18; A5, Fig. 3, clock divider register 22; A8, 4:29-54; A9, 5:21-67). Intel's proposed construction, "control software executing on the processor and the cooperating hardware on the processor," is impermissibly vague and fails to identify any particular structure disclosed in the specification. 5. "a state of said computer processor" Proposed Constructions Transmeta - condition of the computer processor such as activeness or idleness. Intel - the activeness or idleness of the computer processor.

Claim Language "a state of said computer processor" (claim 30)

Transmeta's proposed claim construction is consistent with the claim language and the specification. (A12). The `061 patent's claims and specification provide examples of various states of a computer processor, including halt, sleep and frequency states of operation. (A12, claims 31-33; A9, 5:21-45; A10, 7:49-53). Intel's construction impermissibly narrows "a state of said computer processor" to activeness or idleness, ignoring the other states disclosed in the patent. 6. "said computer processor determining a frequency and a voltage" / "a computer processor determining a voltage-frequency pair" Proposed Constructions Transmeta - No construction necessary ­ plain and ordinary 6

Claim Language "said computer processor

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determining a frequency meaning. and a voltage" (claims 23, Intel - the computer processor itself, not the operating system, 30) determines a frequency and a voltage. "a computer processor Transmeta - No construction necessary ­ plain and ordinary determining a voltagemeaning. frequency pair" (claim Intel ­ a computer processor itself, not the operating system, 39) determines a pair of voltage and frequency values. These terms require no construction, and should be given their plain and ordinary meaning. Intel does not actually construe these terms, but improperly seeks to add the limitation "not the operating system." In the joint claim chart, Intel cites to applicants' arguments made during prosecution that the Horden patent: fails to teach or suggest the claimed limitation of a computer processor determining the frequency and voltage, which is vastly different from an operating system performing these tasks. (A290).1 The Examiner explicitly rejected applicants' arguments, however, stating: [In Horden] [t]he operating system runs on the processor. Thus the processor determines the frequency and voltage at which to operate the processor. ... In Horden the control software is the operating system. (A306). Thereafter, the applicants disavowed their arguments by acquiescing to the Examiner's position and amended the claims in other respects. (A329). Based on these amendments and the remarks discussing and explaining them, the Examiner allowed the issued claims. (A341; B1-3). Therefore, applicants did not rely on the Horden operating system arguments for any purpose, the Examiner explained that the claim language includes the operating system running on the processor, and there is therefore no basis for Intel's proposed limitation. 2

1

Applicant's prosecution statements were factually incorrect and inconsistent with the application's disclosure. Under Intervet Am. v. Kee-Vet Labs., 887 F.2d 1050, 1054 (Fed. Cir. 1989), such factually incorrect statements cannot result in a disclaimer.
2

Intel's proposal should also be rejected because contrary to its position in this litigation, Intel has argued in the `061 reexamination that the claim language includes the processor itself and the operating system running on the processor. (B5).

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7.

"operating conditions of the central processor" / "operating conditions internal to said computer processor" / "internal conditions of a computer processor" Proposed Constructions Transmeta - No construction necessary ­ plain and ordinary meaning. If the Court decides a construction is necessary, this term means a plurality of types of operating conditions that are internal to the computer processor. Intel - a plurality of types of operating conditions, excluding core utilization, that are internal to the computer processor.

Claim Language "operating conditions of the central processor" (claim 8) "operating conditions internal to said computer processor" (claim 15) "internal conditions of a computer processor" (claim 39)

These terms require no construction, and should be given their plain and ordinary meaning. Intel again does not actually construe these terms, but improperly seeks to add the limitation "excluding core utilization." In the joint claim chart, Intel again cites to the Horden operating system arguments that applicants made during prosecution. (A253). As discussed above, these arguments were explicitly rejected by the Examiner and disavowed by applicants. In rejecting applicants' arguments, the Examiner construed the `061 claims, stating: "The core utilization is an internal condition. ... Core utilization includes idle time." (A267). The specification and claims also provide that idle time is an operating condition internal to the computer processor. (A11-12, claims 23, 44-47; A9, 5:21-45). Thus, for the same reasons as discussed in the previous section, there is no basis for adding Intel's proposed limitation. 3

Intel's construction should also be rejected because contrary to its position in this litigation, Intel has argued in the `061 reexamination that core utilization (processor load) is a condition of the processor. (B6).

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B.

The Multiple Typed Register Patents4

Computer processors typically include storage locations on the processor called registers. (A45, 1:53-57). Registers provide temporary storage that the processors can access more quickly than memory located outside of the processor, such as the main memory. There are a variety of types of registers, including, for example, address registers and general purpose registers. (A45, 1:53-57). One type of register that is common to computer processors is a data register. (A45, 1:53-59). Data registers are normally used to hold either integer or floating point data. (A45, 2:4244). Integer data is "numeric data which is used to represent a positive or negative whole number or zero," e.g., "2" or "74." (D.I. 92, Tab A, p. 129). Floating point data, on the other hand, is numeric data that is "represented by a positive or negative sign, the digits in the number, and an exponent, specifying the magnitude of the number, e.g., "-3.0 x 105." (Id). The Multiple Typed Register patents emphasize a shortcoming of prior art as having only one set of registers for a single data type. (A24, 2:41-49). Prior art processors often included one set of registers for holding integer data and a separate set of registers for holding floating point data, "with each set being limited to its respective data type." (See A24, 2:60-65). This arrangement, however, resulted in inefficiencies. (A45, 2:66). Because "user applications frequently involve exclusively integer operations, and perform no floating point operations whatsoever," the separate set of floating point registers often "remain idle during the entire execution." (A25, 3:2-7).

The Multiple Typed Register patents are the `687, `986 and `449 patents. Although there are three separate patents in the family, the specifications are identical; only the claims differ. Therefore, the references herein are made to the `687 patent, with the understanding that they apply equally to the other two patents.

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Recognizing this inefficiency, the Multiple Typed Register patents provide for "an architecture which allows multiple register sets within a given data type," teaching that it is "desirable for a microprocessor's floating point registers to be usable as integer registers." (A25, 3:54-60). The patent accomplishes this with "a plurality of integer register sets" whereby "[o]ne of the register sets is also usable as a floating point register set." (A25, 4:55-63). The specification further explains that "Register Set A" includes "integer registers 24 (RA[31:0]), each of which is adapted to hold an integer value datum," and "Register Set FB" includes "retypable register set FB 20 [which] may be thought of as including floating point registers 48 (RF[31:0]), and/or integer registers 50 (RB[31:0])." (A26, 5:6366, A27, 7:26-30). The two register sets are depicted in Figure 1 (highlighted in yellow). (A15, Fig. 1).

The Multiple Typed Register patents also disclose the use of Switching and Multiplexing Control Units (SMC units) (highlighted in blue above), which determine whether to read or write an operand value in either the integer register set or the floating point register set. (A29, 11:818; see A15, Fig. 1). The SMC units are responsive to bits in an instruction that specify which

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register is to be accessed. (A25, 4:58-60, A28, 10:42-48, A28-29, 10:64-11:4, 11:12-14, 11:5659). Importantly, because the SMC units are connected (as shown in blue above), they allow operands to be moved from one register set to the other. That is, if an operand is read from one register set, the connectivity between the register sets allows the operand to be written to the opposite register set. This type of "register-to-register" instruction is "of particular interest" to these patents. (A28, 9:16-17). Multiplexers, and an integer functional unit, allow connection and flow of data between and to either register set (A25, 4:57-60; A28, 10:64-11:4). In the preferred embodiment, register sets are coupled to receive data from, and send data to, each other on buses 114, 118, 116 and 120 of Figs. 2, 2A, 3, 3A. (A31, 15:21-22, 15:40-42, 15:52-54, 16:1-2, 16:37-39, 16:48-49, 16:56-59; A32, 17:1-5, 17:16-21, 17:39-41). There are sixteen disputed terms in the Multiple Typed Register patents. Transmeta's proposed constructions for all of the disputed terms are provided in D.I. 92, Tab A, pp. 129-143. 1. "central processing unit" / "processor" Proposed Constructions Transmeta ­ No construction necessary ­ plain and ordinary meaning. Intel ­ a processor in a reduced instruction set computer.

Claim Language "central processing unit" / "processor" (`687 claim 1; `986 claim 1; `449 claim 1)

The terms "central processing unit" and "processor" appear in the preamble of the asserted claims and need no construction. (See, e.g., A32, 18:45-48; A76, 18:5). These terms are readily understood by a jury and should be given their ordinary meaning. Intel seeks to limit the claims of the Multiple Typed Register patents to microprocessors having a "Reduced Instruction Set" (RISC) by construing the common terms "central processing unit" and "processor" to mean "a processor in a reduced instruction set computer." (D.I. 92, Tab

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A, p. 129). Intel's proposed construction asks that the Court improperly import a limitation from the specification into the preamble by redefining a term that has an ordinary meaning. See Comark Communs., Inc. v. Harris Corp., 156 F.3d 1182, 1186 (Fed. Cir. 1998). Although some of the unasserted claims specify a RISC processor in the preamble (see, e.g., A54, claim 13), none of the asserted claims recite RISC or any other type of instruction set. (See, e.g., A53, claim 1). Moreover, processors with a complex instruction set (CISC) also have integer registers and floating point registers, and can use the claimed inventions of the Multiple Typed Register patents to improve their performance. (B1010). 2. "first registers each for holding the integer data" and "second registers each for holding the integer data and for holding floating point data" Proposed Constructions Transmeta ­ storage locations identifiable by instructions and capable of storing only integer data. Intel ­ storage locations identifiable by instructions and capable of storing at least integer data. Transmeta ­ each second register can hold integer data and, alternatively, can hold floating point data. Intel ­ storage locations identifiable by instructions and capable of storing at least integer data and floating point data.

Claim Language "first registers each for holding the integer data" (`687 claim 1; `986 claim 1; `449 claim 1) "second registers each for holding the integer data and for holding floating point data" (`687 claim 1; `986 claim 1; `449 claim 1)

The "first registers" and "second registers" in the asserted claims refer to the integer and floating point registers taught by the patent (See, e.g., A32, claim 1). Transmeta's constructions properly define the role of each register set recited in the claims. The first register set is "capable of storing only integer data," and the second register set "can hold integer data and, alternatively, can hold floating point data." (D.I. 92, Tab A, p. 129). Intel's constructions improperly include the phrase "at least," which would eliminate any distinction between the two register sets by allowing either register set to hold either type of data. (D.I. 92, Tab A, p. 129). This ignores the

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context from which the Multiple Typed Register patent arose. The prior art inefficiently devoted one register set to integer data and another register set to floating point data. In contrast to the prior art, the patents allow the floating point registers to also be used for integer data. "first registers." The claims state that the first register set is for holding "the integer data." (e.g., A32, claim 1). The specification teaches that the first register set (or "Register Set A") includes "integer registers 24 (RA[31:0]), each of which is adapted to hold an integer value datum." (A26, 5:63-66) (emphasis added). There is no suggestion that the integer register set can hold any other data type. Indeed, the patent labels Register Set A in Figure 1 as "Integer Registers RA." (A15, Fig. 1; A26, 5:65-66). And during prosecution the patentee explained that integer registers, which are 32 bits long, are ineffective for holding 80-bit floating point data because it would result in a loss of precision. (A363). Intel proposes that the first register set can hold "at least integer data." (D.I. 92, Tab A, p. 129). This construction would improperly allow the integer register set to also hold floating point data, which eliminates the claimed distinction between the two claimed register sets. It is also inconsistent with the language of the claim, which requires the register to hold "the integer data." (See, e.g., A32, claim 1). "second registers." The claims state that the second registers are "each for holding the integer data and for holding floating point data." (See, e.g., A32, claim 1). This refers to the fact that the second registers are capable of holding both types of data. As the specification further explains, at any point in time, "[e]ach individual register in the register set RFB[] may hold

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either a floating point value or an integer value." (A27, 7:42-43). That is, each register in the set can hold integer data or floating point data, but not both at the same time.5 During prosecution of the `687 patent, applicants emphasized the distinction between the two register sets by arguing that the "claimed invention recites an integer register set for storing integer data and a re-typable register set for storing floating point or integer data. Thus, Applicants' claimed invention provides a second source for storing integer operands and results." (A363).6 Accordingly, the intrinsic evidence is consistent with the claim requirement that the first register holds only integer data and the second register holds integer data or, alternatively, floating point data. Intel proposes instead that the second register set can hold "at least integer data and floating point data." (D.I. 92, Tab A, p. 130). But again, there is no suggestion in the claims, specification or file history that the second register can hold any type of data other than what is claimed ­ i.e., integer or floating point data. The intrinsic evidence emphasizes that the advantage of the invention is that the floating point registers are "usable as integer registers in case the available integer registers are inadequate to optimally hold the necessary amount of integer data." (A353; A25, 3:58-60). 3. Claim Language "a field"
5

"a field" . . . "specifying which of the first and second register sets is to be accessed" Proposed Constructions Transmeta ­ one or more bit locations in a computer instruction.

Transmeta's understanding is that the parties do not disagree on this point. However, Intel's proposed construction is ambiguous on this point, and therefore Transmeta's construction should be adopted.

Although these argument were made with respect to other claims, they apply with equal force to the issued claims of the `687 patent. In particular, applicants stated that claim 1 of the `687 patent was allowable because it had been amended to recite "a first register set for storing integer values and a second register set for storing floating point and integer values." (A365).

6

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(`687 claim 1; `986 claim 1) "specifying which of the first and second register sets is to be accessed" (`687 claim 1; `986 claim 1)

Intel ­ a dedicated portion of an instruction having a defined meaning. Transmeta ­ No construction necessary ­ plain and ordinary meaning. If the Court decides a construction is necessary, this term means that the field in the instruction indicates which register set is to be accessed. Intel ­ the instruction is modifiable so that it performs the operation utilizing either of the two register sets.

Because the claimed invention includes multiple register types, instructions executed by the processor must indicate which register is to be accessed. The claims include this element by reciting that "a specific instruction includes a field specifying which of said first and second register sets is to be accessed in response to execution of said specific instruction." (A53, claim 1) (emphasis added). "field." "Field" should be given its ordinary meaning of "one or more bit locations in a computer instruction." A "field" is defined by IEEE as "a set of bit locations in a computer word used to express the address of the operand." (B1003). Figure 7 of the patent provides an exemplary processor instruction that includes a field specifying the register locations from which operands are to be read from or written to. (A23, Fig. 7; A26, 5:31-33). As shown in the figure, the instruction I[] includes multiple bit locations, i.e., B0, B1 and B2, that indicate which register the instruction reads from and writes to. (A23, Fig. 7). Figures 5 and 6 show that the multiple bits B0, B1 and B2 from the instruction field are read by multiplexers S1 and S2 to determine which register to access. (A21, Fig. 5; A22, Fig. 6; A28, 9:21-23, 9:30-34, 9:36-38, 10:64-11:4; A29, 11:12-14). Intel proposes that the field should be limited to a "dedicated portion" of the instruction that has a defined meaning. (D.I. 92, Tab A, p. 130). But Figure 7 shows that the field of the instruction specifying which register to access is not located in a single contiguous portion. Rather, it can be spread across multiple bit locations. Limiting the field of the claims to only one 15

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of those portions would exclude the embodiment of Figure 7 from the claims. Moreover, there is no reason to limit the field to a "dedicated" portion of an instruction. The claims do not prohibit the same field from performing other actions. Nor do they prohibit different fields of different instructions from performing the required function. "specifying which of the first and second register sets is to be accessed." This phrase does not need to be construed and should be given its ordinary meaning. A jury would easily understand that the claim requires the field to specify "which of the first and second register sets is to be accessed." (See, e.g., A32, claim 1). If the Court feels it is necessary to construe this language to assist the jury, Transmeta proposes that it be construed to mean that the field in the instruction indicates which register set is to be accessed. Intel's construction entirely rewrites and changes the meaning of the claim. The claims require a field in the instruction to specify which register set to access. Intel's construction, however, says nothing about the role of the field, or about specifying which register to access. Instead, Intel requires an instruction to be modifiable so that it can perform an operation utilizing either register set. This has no basis and is contrary to the claim language and the specification. The claims call for two separate register sets and a field in the instruction that specifies which set to access. (See, e.g., A32, claim 1). 4. Claim Language "reading means for
7

"reading means . . ." and "writing means . . ."7 Proposed Constructions Transmeta ­ The function performed by the claimed "reading

The `449 patent requires an "execution unit" that "reads an operand value from either said first register [or] second register set as specified by said instruction" or "writes a result value to said first register set or said second register set as specified by said instruction." (See A76, claim 1). Transmeta's proposed constructions for the "execution unit" terms are consistent with its proposed constructions for the functions of the "reading means" and "writing means." Intel has likewise proposed similar constructions. Therefore, Transmeta does not repeat its arguments for those terms in this brief.

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reading an operand value from either the first register set or second register set as specified by the field" (`687 claim 1; `986 claim 1)

"writing mean[s] for writing a result value to the first register set or the second register set as specified by the field" (`687 claim 1; `986 claim 1)

means" is reading an operand value from either the first register set or second register set as specified by the field. The disclosed structures that correspond to the function of the claimed reading means is the multiplexing circuitry within the SMC units A and B (for SMC unit A, see those S1/S2 MUXs that participate in the selection between register sets; for SMC Unit B, see those S1/S2 MUXs that participate in the selection between register sets). Intel ­ The claimed function is "reading data in response to an instruction that is modifiable to perform an operation utilizing either of the two register sets for source data." The corresponding structure includes at least the 12 multiplexers labeled S1, S2 in figures 2A and 3A. The multiplexers are controlled by instruction bits B1 (SOURCE 1) and B2 (SOURCE 2). Transmeta ­ The function performed by the claimed "writing means" is for writing a result value to the first register set or the second register set as specified by the field, and which is capable of writing a result value to the first register set if the reading means reads an operand value from the second register set, and vice versa. The disclosed structure in the patent specification that correspond to the function of the claimed "writing means" is multiplexing circuitry within the SMC units A and B (for SMC unit A, see MUX circuits 148; for SMC unit B, see MUX circuits 110). Intel ­ The claimed function is "writing data in response to an instruction that is modifiable to perform an operation utilizing either of two register sets for destination data." The corresponding structure includes at least the 4 multiplexers labeled 110- , 110- , 148- , and 148- in figures 2 and 3. The multiplexers are controlled by instruction bit BO (DEST.) of figure 7.

The parties agree that the terms "reading means" and "writing means" recite means-plusfunction elements that must be construed according to 35 U.S.C. §112, ¶6. The Claimed Function of the "reading means." The claims recite the function of the reading means as "reading an operand value from either the first register set or second register set as specified by the field." (See, e.g., A32, claim 1). Transmeta's construction of the claimed function is identical to the claim language. (D.I. 92, Tab A, p. 131). Intel's construction improperly requires the reading means to read data "in response to an instruction that is modifiable to perform an operation utilizing either of the two register sets for source data." (D.I. 92, Tab A, p. 131). This additional limitation is not called for by the claim 17

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language or by the specification. The claims expressly state that the reading means selects one of the registers "as specified by the field." There is no support for requiring "an instruction that is modifiable." The Claimed "reading means." Because the reading means must be capable of reading an operand from either the first register set or second register set, only those multiplexers S1 and S2 that participate in the selection between register sets should be included in the structure. Micro Chem., Inc. v. Great Plains Chem. Co., 194 F.3d 1250, 1258 (Fed. Cir. 1999) (35 U.S.C. §112, ¶6 does not "permit incorporation of structure from the written description beyond that necessary to perform the claimed function."). Figures 5 and 6 of the patent depict multiplexing circuitry S1 and S2 within SMC units A and B that is responsive to the field and selects between the two register sets. (A31, 16:6-15; A32, 17:49-50; e.g., A21, Fig. 5; A22, Fig. 6). Figures 5 and 6 show multiplexers S1 and S2 receiving bits B1 and B2 and, depending upon the value of the bits, selecting between one of the registers in integer register set (RA[]) or floating point register set (RFB[]). (A21, Fig. 5; A22, Fig. 6). As shown in Figures 5 and 6, not all of the multiplexers S1 and S2 are able to read from either register set. (A21, Fig. 5; A22, Fig. 6). The top two multiplexers S1 and S2 in Figure 5, for example, are only connected to floating point registers RFB2, RFB0, RFB1 and RFB3. (A32, Fig. 5). These multiplexers should not be included in the claimed "reading means" because they are not capable of reading an operand value from either the floating point register set RFB[] or the integer register set RA[]. Intel's construction should be rejected because it requires all 12 multiplexers labeled S1 and S2 to be part of the structure, including those that are incapable of reading from the integer register set. Intel also adds a requirement that the multiplexers are controlled by instruction bits

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B1 (SOURCE 1) and B2 (SOURCE 2). This additional functional limitation is not called for by the claims which require only that the reading means read from a register that is specified by the field. The Federal Circuit has instructed that §112, ¶6 "does not permit limitation of a meansplus-function claim by adopting a function different from that explicitly recited in the claim." Micro Chemical, 194 F.3d at 1258. The Claimed Function of the "writing means." The claim recites that the function of the "writing mean[s]" is "writing a result value to the first register set or the second register set as specified by the field." (See, e.g., A32, claim 1). The patent also indicates that the writing means must be further capable of writing a result value to the first register set if the reading means reads an operand value from the second register set, and vice versa. This is required in order to fully satisfy the expressed object of the invention of the Multiple Typed Register patents of having "an architecture which allows multiple register sets within a given data type." (A25, 3:54-56; also, 4:54-62). In order to realize this capability, the patents disclose an architecture that allows the register sets to freely transfer the integer values from one register set to another. (4:57-60; 10:64-11:4). In the preferred embodiment, register sets are coupled exchange data via buses 114, 118, 116 and 120 of Figs. 2, 2A, 3, 3A. (A31, 15:21-22, 15:40-42, 15:52-54, 16:1-2, 16:37-39, 16:48-49, 16:56-59; A32, 17:1-5, 17:16-21, 17:39-41). As with the "reading means," Intel's proposed construction of "writing means" requires "an instruction that is modifiable to perform an operation utilizing either of the two register sets for source data." (D.I. 92, Tab A, p. 132). This additional limitation is improper for the same reasons discussed above. The Claimed "writing means." The parties agree that the specification discloses multiplexing circuitry 148 and 110 within the SMC units A and B, which is capable of writing to

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the first and second register sets, respectively. (A31, 16:35-38, 15:20-23; see also A16, Fig. 2; A18, Fig. 3). This circuitry performs the claimed function of writing to the register that is specified by the instruction field. The circuitry is also capable of writing to the opposite type of register than the register type that is read from. Indeed, the specification points out that "register-to-register" instructions are an "[i]nstruction class of particular interest to this Application." (A28, 9:16-17). As with the reading means, Intel's construction requires all "4 multiplexers labeled 110- , 110- , 148- , and 148- in figures 2 and 3" to be part of the disclosed structure. (See D.I. 92, Tab A, p. 132). Intel also adds a requirement that "the multiplexers are controlled by instruction bit B0 (DEST.) of figure 7." (D.I. 92, Tab A, p. 132). For the same reasons discussed with respect to the "reading means," Intel's construction should be rejected. 5. "read access means" and "write access means"

Proposed Constructions Transmeta ­ The function performed by the claimed "read access means" is accessing a register set to retrieve data from a given register. The disclosed structures that correspond to the function of the claimed reading means is the multiplexing circuitry within the SMC units A and B (for SMC unit A, see MUXs 150; for SMC Unit B, see MUXs 112). Intel ­ The claimed function is "obtaining source data from a register set." The corresponding structure includes at least the 12 multiplexers labeled S1, S2 in figures 2A and 3A. The multiplexers are controlled by instruction bits B1 (SOURCE 1) and B2 (SOURCE 2). "write access means, Transmeta ­ The function performed by the claimed "write access responsive to the data means" is accessing a register set to store into a given register data processing system specified by said write operation. The disclosed structure in the performing a given write patent specification that correspond to the function of the claimed operation, for accessing "writing means" is multiplexing circuitry within the SMC units A said register set to store and B (for SMC unit A, see MUX circuits 148; for SMC unit B, see into a given register" MUX circuits 110).
8

Claim Language "read access means, responsive to the data processing system performing a given read operation of a specific data type, for accessing said register set to retrieve data from a given register" (`986 claim 11)8

This language appears in claim 6 from which claim 11 depends. (A53-54).

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(`986 claim 11)

Intel ­ The claimed function is storing result data to the register set. The corresponding structure includes at least the 4 multiplexers labeled 110- , 110- , 148- , and 148- in figures 2 and 3. The multiplexers are controlled by instruction bit (DEST.) of figure 7.

The Claimed Functions of the "read access" and "write access" Means. In contrast to the reading and writing means of claim 1, the "read access means" and "write access means" in claim 11 of the `986 patent do not need to be capable of reading from or writing to either register set. Rather, the claim requires that the "access means" provide access to a single register set containing a specific data type. The claim states that the "read access means [is] responsive to the data processing system performing a given read operation of a specific data type." (A53, claim 11) (emphasis added). The claimed functions, therefore, are "accessing a register set to": (i) "retrieve data from a given register," in the case of the read access means, and (ii) "store into a given register data specified by said write operation," in the case of the write access means. (D.I. 92, Tab A, pp. 136-37). The Claimed "read access means." Because the read access means need only read from "a given register," and not from either register type, the corresponding structure is not ­ as Intel suggests ­ the multiplexing circuitry S1 and S2. As discussed above, multiplexers S1 and S2 are capable of reading from either register set. Instead, the specification discloses multiplexing circuitry 112 (shown in Figure 2A) for reading from Register Set RFB and multiplexing circuitry 150 (shown in Figure 3A) for reading from Register Set RA. (A17, Fig. 2A; A19, Fig. 3A; A31, 15:33-35, 15:47-53, 16:42-44). Multiplexers 112 and 150 are the corresponding structure in the specification that is used for retrieving data from a given register set. The Claimed "write access means." The parties agree that the structure corresponding to the claimed "write access means" is multiplexing circuitry 110 and 148 (in Figures 2 and 3). (A37, Fig. 2; A39, Fig. 3; see D.I.92, Tab A, pp.137-38). Intel's construction, however, includes

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the same extraneous limitations as its construction for "writing means," i.e., "at least the 4 multiplexers" and "controlled by instruction bit (DEST.) of figure 7." (D.I. 92, Tab A, p. 137). For the reasons discussed above, these additional limitations are improper. 6. Claim Language "Boolean execution unit" (`986 claim 11) Boolean Execution Unit Terms Proposed Constructions Transmeta ­ circuitry that executes instructions that generate Boolean results. Intel ­ a functional unit that is only used in performing bitwise logical combinations of Boolean register contents according to Boolean functions. Transmeta ­ instructions that perform Boolean operations on one or more Boolean values. Intel ­ instructions that perform Boolean operations on the results of previous Boolean operations. Transmeta ­ one or more bits representing logical "true" or "false" values. Intel ­ a single bit true/false indication from a Boolean function.

"Boolean combinational instructions each operating on one or more Boolean operands" (`986 claim 11) "Boolean result" (`986 claim 11)

In addition to the integer register set, and the retypable integer/floating point register set, the Multiple Typed Register patents disclose the use of a third set of registers called "Boolean registers." These registers are used for holding Boolean results and are associated with a Boolean execution unit. Similar to the "execution unit" in claim 1 of the `449 patent (which was an agreed upon term between the parties, see D.I. 92, Tab A, p. 141), the Boolean execution unit is "circuitry that executes instructions that generate Boolean results." (D.I. 92, Tab A, p. 138). Claim 11 of the `986 patent also specifies that the Boolean execution unit executes "Boolean combinational instructions each operating on one or more Boolean operands" (A54, claim 11). Transmeta proposes that this claim language means what it says -- "instructions that perform Boolean operations on one or more Boolean values." (D.I. 92, Tab A, pp. 138-39). Intel, however, seeks to import an additional limitation by requiring the claimed "Boolean

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operands" to result from "previous Boolean operations." (D.I. 92, Tab A, pp. 138-39). This contradicts the preferred embodiment, which provides that the Boolean execution unit also comprises a "numerical execution means for executing numerical comparison instructions to compare two multi-bit numerical operands." (A54, 19:36-39). Such comparisons are made on integers or floating point numbers, not Boolean values. (A28, 9:41-44). However, they do yield Boolean results, which in turn can be the operands in Boolean operations. (A29, 11:65-12:2). Therefore, Intel's "previous Boolean operations" requirement is too restrictive. Finally, Intel seeks to limit the claimed "Boolean result" to "a single bit." (D.I. 92, Tab A, p. 139). Presumably, Intel bases this limitation on the embodiment in the specification where "each Boolean register is one bit wide, indicating one Boolean value." (A27, 8:31-33) (emphasis added). But the specification also teaches that Boolean functions can "perform[] bitwise logical combinations of Boolean register contents." (A29, 12:5-8). A bitwise logical combination necessarily requires multiple bits. Thus, in one disclosed embodiment, the Boolean register is typically multiple bits wide, and the Boolean result of a bitwise logical combination of these Boolean registers would comprise multiple bits, not a single bit. (A32, 7:66-8:1). C. The Register Renaming Patents9

The claims of the Register Renaming patents are directed to improving the speed of execution of out-of-order instructions in a processor. (A88, 1:44-47). Processors that can execute multiple instructions in parallel are called superscalar. Superscalar processors include the ability to issue and execute instructions out-of-order from the program order. (A88, 1:44-47; A994). Processors using superscalar techniques, therefore, are generally faster than those
9

The Register Renaming patents are the `624, `526 and `433 patents. Although there are three separate patents in the family, the specifications are identical; only the claims differ. Therefore, the references herein are made to the `624 patent, with the understanding that they apply equally to the other two patents.

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processors that can only execute instructions serially, i.e., executing one instruction after another. A processor with a reduced instruction set (RISC) is an example of a processor with superscalar and "out-of-order" capabilities. (A88, 1:44-47). Processors with a complex instruction set (CISC) may also have superscalar capabilities, including the capability for out-of-order execution of instructions. (A992; A1004). Although the embodiments of the Register Renaming patent inventions are described with reference to a RISC processor, the invention and its applications are not limited for use in RISC processors. (A992). The claimed inventions use a combination of three features to improve out-of-order execution in a processor: (1) data dependency checking; (2) register renaming; and (3) instruction scheduling. (A88, 1:47-49; A90-91, 6:18-7:16). Figure 1 of the specification illustrates the preferred embodiment. (A79, Fig. 1; A91, 7:26-27). To execute a program instruction, the processor fetches instructions for execution. Once decoded, the instructions are organized into a group. (A79, Fig. 1; A91, 7:63-67). The group of decoded instructions is known as an instruction window. (A79, Fig. 1; A91, 7:63-8:10). Instructions remain in the window until the processor resolves the dependencies between the instructions. (A90, 6:40-45; A91, 8:6-

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10, 8:56-59). Data dependency checking is a process in which a device (data dependency checker) compares an instruction with another instruction and determines if there are any dependencies. (A90, 6:36-37). For example, a program might issue an instruction to add two numbers followed by an instruction to multiply the result of the previous instruction with a third number. The multiplication instruction is said to be dependent on the addition instruction because the multiplication instruction cannot be performed until after the addition instruction has completed. The result of the addition instruction can be considered an input required by the multiplication instruction. (See A90, 6:40-44). Once dependencies are resolved, the results of instructions move from temporary buffers (A79, Fig. 1, 116) to an appropriate place in the register files (A79, Fig. 1, 117). This movement process is called "retirement." (A91, 8:59-61). In the preferred embodiment, at least a portion of the instructions in the instruction window are checked for dependencies and then their results are assigned temporary storage locations in temporary buffers. (A91, 8:30-34, 42-46; A94, 13:6-10). If a dependency exists, the tag assign logic unit outputs a name for the temporary buffer location (also called a tag) and assigns that tag to the input required by the dependent instruction. (A90, 6:46-49, 55-63; A94, 13:6-7). The tags indicate the physical storage locations of the inputs for instructions. (A90, 6:62-63; A94, 13:7-10). Instructions access the contents of the temporary buffers by using the tags as a locator of the physical storage where the input data for each instruction is to be found. (A91, 8:15-19; A94, 13:44-62). The tags, therefore, rename the input register names identified in the instruction, and can name multiple physical registers for the same input register. (A94, 13:44-62; A460).

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The instructions in the window can also be pre-assigned to locations in the temporary buffer in program order before being checked for dependencies. The instructions are then checked for dependencies and if a dependency exists, the dependency checker outputs the tag of the previously assigned temporary buffer location. (A96, claim 1). 1. "register renaming" Proposed Constructions Transmeta ­ naming multiple physical registers for the same architectural register in order to reduce or eliminate storage conflicts. Intel ­ removing storage conflicts without actually renaming register addresses in the instruction.

Claim Language "register renaming" (`624 claims 1, 13; `433 claims 1, 13)10

The term "register renaming" appears in the preamble of the asserted claims of the `624 and `433 patents. For example, the preamble of `624, claim 1 states: "A system for register renaming in a computer system capable of out-of-order instruction execution, comprising:" (A96, claim 1). Transmeta's proposed construction is the commonly understood meaning of register renaming. (B1098). Register renaming means "naming multiple physical registers for the same architectural register in order to reduce or eliminate storage conflicts."11 (e.g., D.I. 92, Tab A, p. 144; see also B1098). Register renaming allows the duplication of registers by allowing one architectural register name to refer to data residing in multiple physical registers. (See A88, 6:11-18; A89, 3:19-30; A996). This meaning is set forth in the specification: Anti- and output dependencies are more properly called "storage conflicts" because reusing storage locations (including registers) causes instructions to interfere with one another even though conflicting instructions are otherwise
10

"Register renaming" also appears in claims 7, 14, 15, 16 and 19 of the `624 patent, and claims 2, 3, 4, 6, 7, 14, 15, 16 and 19 of the `433 patent.

11

An architectural register is a register name referred to by the program that runs on a microprocessor. (B1098).

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independent. Storage conflicts constrain instruction issue and reduce performance. But storage conflicts, like other resource conflicts, can be reduced or eliminated by duplicating the troublesome resource. (A88, 2:11-18) (emphasis added). The specification, therefore, explains register renaming as "duplicating the troublesome resource," ­ i.e., naming additional physical registers with the same architectural register name so that instructions using that same architectural register can be executed in parallel. (See A88, 2:16-18; A89, 3:19-30, 52-56). The specification similarly explains that the same register identifier, i.e., the same architectural register name, may be used to access different physical registers: "The same register identifier in several different instructions may access different hardware registers, depending on the locations of register references with respect to register assignments." (A89, 3:27-30; see also A89, 3:19-22). The specification is consistent with the common understanding of register renaming. (see A996; B1098). Intel's proposed construction does not define what register renaming is. Instead, Intel adds a negative limitation to the preamble of the claim that prohibits the invention from "actually renaming register addresses in the instruction." (See D.I. 92, Tab A, p. 144). Contrary to Intel's proposed construction, the invention does not operate without renaming addresses "in the instruction." Rather, the specification teaches that: A Register Rename Circuit (RRC), which is part of the scheduling logic of the computer's IEU performs this function by locating dependencies between current instructions and then renaming the sources (inputs) of the instruction. (A91, 8:15-19) (em