Free Claim Construction Opening Brief - District Court of Delaware - Delaware

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IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF DELAWARE TRANSMETA CORPORATION, Plaintiff and Counterclaim Defendant, Civil Action No. 06-633-GMS v. INTEL CORPORATION, Defendant and Counterclaim Plaintiff.

INTEL CORPORATION'S OPENING CLAIM CONSTRUCTION BRIEF John W. Shaw (No. 3362) Karen L. Pascale (No. 2903) YOUNG CONAWAY STARGATT & TAYLOR, LLP The Brandywine Building 1000 West Street, 17th Floor Wilmington, DE 19801 (302) 571-6600 [email protected] Attorneys for Defendant Intel Corporation OF COUNSEL: Matthew D. Powers Jared Bobrow Steven S. Cherensky WEIL, GOTSHAL & MANGES LLP 201 Redwood Shores Parkway Redwood Shores, CA 94065 (650) 802-3000 Kevin Kudlac WEIL, GOTSHAL & MANGES LLP 8911 Capital of Texas Highway, Suite 1350 Austin, TX 78759 (512) 349-1930 Dated: October 19, 2007

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TABLE OF CONTENTS Page(s) INTRODUCTION..................................................................................................................... 1 LEGAL FRAMEWORK ........................................................................................................... 3 A. General Principles of Claim Construction........................................................... 3 1. 2. 3. B. I. The Specification Is The "Single Best Guide" To Claim Construction ........................................................................................... 3 Statements Made During Prosecution May Also Limit The Claims ......... 4 Extrinsic Evidence Is Generally "Less Reliable" ..................................... 5

Construction of Means-Plus-Function Terms...................................................... 5

ARGUMENT ............................................................................................................................ 6 THE TRANSMETA PATENTS-IN-SUIT ..................................................................... 6 A. THE SEIKO EPSON REGISTER RENAMING PATENTS ............................... 6 (a) (b) 2. (a) The Problem Addressed By The Register Renaming Patents........ 7 The Invention Claimed In The Register Renaming Patents .......... 8 The Specification Consistently And Repeatedly Describes The Instruction Window As The Group Of Instructions Compared Against Each Other For True Dependencies ............... 9 The Instruction Window Must Be The Same Size As The Temporary Buffer For The One-To-One Mapping Scheme To Work.................................................................................... 10 Transmeta's Construction Is Inconsistent With The Preferred Embodiment............................................................... 11

The "instruction window" terms (Renaming Terms 3 and 11) ................. 9

(b)

(c) 3. 4. 5. 6. 7. 8.

The "determined by" and "assigned to" terms (Renaming Terms 4, 10, 12, 15, 17, and 18)........................................................................... 12 The "computer system" terms (Renaming Terms 2 and 14; MultiType Terms 1 and 17) ........................................................................... 14 The "register renaming" terms (Renaming Terms 1, 13, and 16) ........... 16 "data dependency checker" (Renaming Term 6).................................... 17 Method Claims 1, 2, And 34 Of The '526 Patent Must Be Performed In The Recited Order ........................................................... 17 The Means-Plus-Function Terms .......................................................... 18 (a) "tag assignment means for receiving data dependency results . . . and outputting a tag . . ." (Renaming Term 9) ........... 18

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TABLE OF CONTENTS (continued) Page(s) (b) (c) B. 1. 2. 3. 4. 5. 6. 7. "means for passing . . . " (Renaming Term 8) ............................ 19 "means for transferring . . ." (Renaming Term 7)....................... 19

THE SEIKO EPSON MULTI-TYPE REGISTER PATENTS........................... 20 Introduction to the Multi-Type Register Patents .................................... 20 "specifying which . . . register set" (Multi-Type Term 7) ...................... 21 "a field" (Multi-Type Term 6)............................................................... 22 "first registers" (Multi-Type Term 3) .................................................... 23 "second registers" (Multi-Type Term 5)................................................ 24 The "processor" terms (Multi-Type Terms 1 and 17) ............................ 25 The "Boolean" terms............................................................................. 25 (a) (b) (c) 8. (a) (b) 9. "Boolean combinational instructions" (Multi-Type Term 15)............................................................................................. 25 "Boolean execution unit" (Multi-Type Term 14) ....................... 26 "Boolean result" (Multi-Type Term 16)..................................... 26 "execution unit . . . accesses" (Multi-Type Term 19) ................. 27 "execution unit . . . reads" and "execution unit . . . writes" (Multi-Type Terms 20 and 21) .................................................. 27 The "reading means" and "writing means" terms (MultiType Terms 9, 10, 12 and 13) .................................................... 28 "means . . . for accessing" (Multi-Type Term 8) ........................ 29

The "execution unit" terms ................................................................... 27

The Means-Plus-Function Terms .......................................................... 27 (a) (b)

C.

THE BELGARD ADDRESS TRANSLATION PATENTS .............................. 30 1. Introduction To The Belgard Address Translation Patents..................... 30 (a) (b) 2. The Prior Art: Two-Step Address Translation........................... 31 The Claimed Invention: One-Step Address Translation ............ 32

Each Of The Asserted Claims Should Be Construed To Require A Page Frame Memory Accessible Based On Virtual Address Information Alone................................................................................. 33 The "memory access" terms (Belgard Terms 11, 21, 32, 37, 42, 46, 61, 77, and 79) ...................................................................................... 34 The "physical address" and "fast physical address" terms ..................... 36 ii

3. 4.

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TABLE OF CONTENTS (continued) Page(s) (a) (b) 5. 6. D. The "physical address" terms (Belgard Terms 1, 16, 25, and 44)............................................................................................. 37 The "fast physical address" terms (Belgard Terms 10, 20, 36, 45, 64, 80, and 86) ............................................................... 38

The "fast page frame" terms (Belgard Terms 4, 12, 23, 29, 34, 39, 41, 43, 47, 49, 50, 51, 58, 60, 67, 68, 73, 74, 78, 81, 85, and 88) ........... 39 The "fast page offset" terms (Belgard Terms 24, 30, 33, 38, 40, 69, 75, and 83)............................................................................................ 40 Introduction To The Power Management Patent.................................... 41 "internal conditions" (Power Management Terms 5 and 10).................. 42 "state" (Power Management Term 8) .................................................... 43 "clock frequency generator" (Power Management Term 3) ................... 44 "processor determining" (Power Management Terms 7 and 11) ............ 45 "determining . . . maximum[s and a] . . . minimum" (Power Management Term 1)............................................................................ 45 "determining a frequency and a voltage" (Power Management Terms 2 and 6)...................................................................................... 47 "means for detecting . . . and causing" (Power Management Term 4) .......................................................................................................... 48

THE TRANSMETA POWER MANAGEMENT PATENT .............................. 41 1. 2. 3. 4. 5. 6. 7. 8.

II.

THE INTEL PATENTS-IN-SUIT................................................................................ 49 A. THE INTEL POWER MANAGEMENT PATENT .......................................... 49 1. 2. 3. 4. 5. B. 1. 2. 3. Introduction To The Intel Power Management Patent............................ 49 The "supplies to" and "provides to" terms (Intel Power Management Terms 2 and 4)................................................................. 50 "electronic device" (Intel Power Management Term 1) ......................... 51 "event" (Intel Power Management Term 6) ........................................... 51 "thermal band" (Intel Power Management Term 8) ............................... 52 Introduction To The Intel Address Translation Patents .......................... 53 "linear address" (Intel Address Translation Term 1).............................. 54 "physical address" (Intel Address Translation Term 4).......................... 54 iii

THE INTEL ADDRESS TRANSLATION PATENTS ..................................... 53

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TABLE OF CONTENTS (continued) Page(s) 4. The "paging" terms ............................................................................... 55 (a) (b) 5. C. "paging" (Intel Address Translation Term 5) ............................. 55 "page frame" and "page frame size" (Intel Address Translation Terms 6 and 7)........................................................ 56

"control unit" and "paging unit" (Intel Address Translation Terms 2 and 3)................................................................................................. 56 Introduction To The Intel Multimedia Processing Patents ..................... 57 "Packed Data" (Intel Multimedia Term 1) ............................................ 57 "copying" and "decoding" (Intel Multimedia Terms 2 and 4)................ 58 " . . . two, four, or eight data elements" (Intel Multimedia Term 5)........ 58 The "intermediate" terms (Intel Multimedia Terms 6, 7, and 8)............. 59

Intel Multimedia Processing Patents ................................................................. 57 1. 2. 3. 4. 5.

CONCLUSION ....................................................................................................................... 60

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TABLE OF AUTHORITIES Page(s) Cases Alloc, Inc. v. ITC, 342 F.3d 1361 (Fed. Cir. 2003) .................................................................... 34 Altiris, Inc. v. Symantec Corp., 318 F.3d 1363 (Fed. Cir. 2003) ................................................ 18 Asyst Techs., Inc. v. Empak, Inc., 268 F.3d 1364 (Fed. Cir. 2001) ............................................ 48 Bicon, Inc. v. Straumann Co., 441 F.3d 945 (Fed. Cir. 2006) .................................................... 29 Chimie v. PPG Indus., Inc., 402 F.3d 1371 (Fed. Cir. 2005) ............................................... 11, 23 Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448 (Fed. Cir. 1998) ............................................... 3 Default Proof Credit Card Sys., Inc. v. Home Depot U.S.A., Inc., 412 F.3d 1291 (Fed. Cir. 2005) ......................................................................................................................................... 5, 48 Demand Machine Corp. v. Ingram Indus., Inc., 442 F.3d 1331, 1340 (Fed. Cir. 2006)................ 4 E-Pass Technologies, Inc. v. 3Com Corp., 473 F.3d 1213 (Fed. Cir. 2007) ............................... 18 Gart v. Logitech, Inc., 254 F.3d 1334 (Fed. Cir. 2001).............................................................. 50 Gaus v. Conair Corp., 363 F.3d 1284 (Fed. Cir. 2004) ............................................................. 11 Georgia-Pacific Corp. v. U.S. Gypsum Co., 195 F.3d 1322 (Fed. Cir. 1999)............................. 24 Honeywell Int'l, Inc. v. ITT Indus., 452 F.3d 1312 (Fed. Cir. 2006) ...................................... 4, 15 J.T. Eaton & Co. v. Atlantic Paste & Glue Co., 106 F.3d 1563 (Fed. Cir. 1997) ....................... 38 JVW Enter., Inc. v. Interact Accessories, Inc., 424 F.3d 1324 (Fed. Cir. 2005)............................ 5 Loral Fairchild Corp. v. Sony Corp., 181 F.3d 1313 (Fed. Cir. 1999) ....................................... 18 Mantech Envt'l Corp. v. Hudson Envt'l Servs., Inc., 152 F.3d 1368 (Fed. Cir. 1998) ................ 46 Old Town Canoe Co. v. Confluence Holdings Corp., 448 F.3d 1309 (Fed. Cir. 2006)............................................................................................... 5 Omega Eng'g v. Raytek Corp., 334 F.3d 1314 (Fed. Cir. 2003) ................................................ 24 On-Demand Machine Corp. v. Ingram Indus., Inc. 442 F.3d 1331 (Fed. Cir. 2006).............. 4, 48 Ormco Corp. v. Align Tech., Inc., 498 F.3d 1307 (Fed. Cir. 2007) .............................5, 13, 31, 34 Personalized Media Comm., LLC v. Int'l Trade Comm'n, 161 F.3d 696 (Fed. Cir. 1998).5, 19, 27

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TABLE OF AUTHORITIES (continued) Page(s) Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) ..................................................... passim Sage Prods. v. Devon Indus., Inc., 126 F.3d 1420 (Fed. Cir. 1997) ....................................... 5, 27 SciMed Life Sys. v. Advanced Cardiovascular Sys., 242 F.3d 1337 (Fed. Cir. 2001) ........4, 15, 45 Springs Window Fashions LP v. Novo Indus., LP, 323 F.3d 989 (Fed. Cir. 2003) ..................... 43 Std. Oil Co. v. Am. Cyanamid Co., 774 F.2d 448 (Fed. Cir. 1985)............................................... 5 Verizon Servs. Corp. v. Vonage Holdings Corp., -- F.3d. --, C.A. Nos. 2007-1240, -1274, 2007 U.S. App. LEXIS 22737 (Fed. Cir. Sept. 26, 2007)............................................................... 15 Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576 (Fed. Cir. 1996)........................................ 56 Watts v. XL Sys., Inc., 232 F.3d 877 (Fed. Cir. 2000) ................................................................ 15

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= TABLE OF ABBREVIATIONS "JA-A" "JA-B" "JA-C" "JA-D" "JA-E" "JA-F" '624 '526 '433 '687 '986 '449 '503 '733 '668 '699 '061 '375 '554 '605 '101 '275 '634 '529 "FH" Joint Appendix Part A Joint Appendix Part B Joint Appendix Part C Joint Appendix Part D Joint Appendix Part E Joint Appendix Part F U.S. Patent No. 5,737,624 U.S. Patent No. 5,974,526 U.S. Patent No. 6,289,433 U.S. Patent No. 5,493,687 U.S. Patent No. 5,838,986 U.S. Patent No. 6,044,449 U.S. Patent No. 5,895,503 U.S. Patent No. 6,226,733 U.S. Patent No. 6,430,668 U.S. Patent No. 6,813,699 U.S. Patent No. 7,100,061 U.S. Patent No. 5,745,375 U.S. Patent No. 5,617,554 U.S. Patent No. 5,802,605 U.S. Patent No. 5,819,101 U.S. Patent No. 5,881,275 U.S. Patent No. 6,385,634 U.S. Patent No. 6,418,529 File History (JA-A at 077-97) (JA-A at 098-119) (JA-A at 120-41) (JA-A at 014-33) (JA-A at 034-55) (JA-A at 056-76) (JA-A at 142-57) (JA-A at 158-74) (JA-A at 175-88) (JA-A at 189-201) (JA-A at 001-13) (JA-D at 001-10) (JA-D at 011-34) (JA-D at 035-57) (JA-D at 058-86) (JA-D at 087-114) (JA-D at 115-35) (JA-D at 136-58)

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TABLE OF REFERENCES TO JOINT CLAIM CONSTRUCTION CHART

A.

SEIKO-EPSON REGISTER RENAMING FAMILY

Joint Claim Construction Chart Tab A, Page Number

The "instruction window" terms: Register Renaming Term 3.......................................................................................... 144 Register Renaming Term 11........................................................................................ 154 The "determined by" and "assigned to" terms: Register Renaming Term 4.......................................................................................... 145 Register Renaming Term 10........................................................................................ 151 Register Renaming Term 12........................................................................................ 155 Register Renaming Term 15........................................................................................ 158 Register Renaming Term 17........................................................................................ 165 Register Renaming Term 18........................................................................................ 169 The "computer system" terms: Register Renaming Term 2................................................................................................ Register Renaming Term 14........................................................................................ 157 The "register renaming" terms: Register Renaming Term 1.......................................................................................... 144 Register Renaming Term 13........................................................................................ 156 Register Renaming Term 16........................................................................................ 159 "data dependence checker" Register Renaming Term 6.......................................................................................... 146 The means-plus-function terms: Register Renaming Term 7.......................................................................................... 146 Register Renaming Term 8.......................................................................................... 148 Register Renaming Term 9.......................................................................................... 149 B. THE SEIKO EPSON MULTI-TYPE REGISTER FAMILY

"specifying which . . . register set": Multi-Type Term 7...................................................................................................... 130 "a field": Multi-Type Term 6...................................................................................................... 130 "first registers": Multi-Type Term 3...................................................................................................... 129

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TABLE OF REFERENCES TO JOINT CLAIM CONSTRUCTION CHART Joint Claim Construction Chart Tab A, Page Number "second registers": Multi-Type Term 5...................................................................................................... 130 The "processor" terms: Multi-Type Term 1...................................................................................................... 129 Multi-Type Term 17.................................................................................................... 141 The "Boolean" terms: Multi-Type Term 14.................................................................................................... 138 Multi-Type Term 15.................................................................................................... 139 Multi-Type Term 16.................................................................................................... 140 The "execution unit" terms: Multi-Type Term 19.................................................................................................... 142 Multi-Type Term 20.................................................................................................... 142 Multi-Type Term 21.................................................................................................... 143 The means-plus-function terms: Multi-Type Term 8...................................................................................................... 131 Multi-Type Term 9...................................................................................................... 131 Multi-Type Term 10.................................................................................................... 132 Multi-Type Term 12.................................................................................................... 136 Multi-Type Term 13.................................................................................................... 137 C. THE BELGARD ADDRESS TRANSLATION FAMILY

The "memory access" terms: Belgard Term 11 ........................................................................................................... 20 Belgard Term 21 ........................................................................................................... 31 Belgard Term 32 ........................................................................................................... 39 Belgard Term 37 ........................................................................................................... 46 Belgard Term 42 ........................................................................................................... 56 Belgard Term 46 ........................................................................................................... 62 Belgard Term 61 ........................................................................................................... 80 Belgard Term 77 ......................................................................................................... 102 Belgard Term 79 ......................................................................................................... 110 The "physical address" terms: Belgard Term 1 ............................................................................................................. 11 Belgard Term 16 ........................................................................................................... 26 Belgard Term 25 ........................................................................................................... 35

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TABLE OF REFERENCES TO JOINT CLAIM CONSTRUCTION CHART

Joint Claim Construction Chart Tab A, Page Number Belgard Term 44 ........................................................................................................... 59 Belgard Term 59 ........................................................................................................... 76 The "fast physical address" terms: Belgard Term 10 ........................................................................................................... 16 Belgard Term 20 ........................................................................................................... 29 Belgard Term 36 ........................................................................................................... 44 Belgard Term 45 ........................................................................................................... 61 Belgard Term 64 ........................................................................................................... 84 Belgard Term 80 ......................................................................................................... 112 Belgard Term 86 ......................................................................................................... 125 The "fast page frame" terms: Belgard Term 4 ............................................................................................................. 19 Belgard Term 12 ........................................................................................................... 21 Belgard Term 23 ........................................................................................................... 32 Belgard Term 29 ........................................................................................................... 37 Belgard Term 34 ........................................................................................................... 41 Belgard Term 39 ........................................................................................................... 51 Belgard Term 41 ........................................................................................................... 54 Belgard Term 43 ........................................................................................................... 57 Belgard Term 47 ........................................................................................................... 64 Belgard Term 49 ........................................................................................................... 66 Belgard Term 50 ........................................................................................................... 68 Belgard Term 51 ........................................................................................................... 70 Belgard Term 58 ........................................................................................................... 75 Belgard Term 60 ........................................................................................................... 78 Belgard Term 63 ........................................................................................................... 84 Belgard Term 67 ........................................................................................................... 91 Belgard Term 68 ........................................................................................................... 92 Belgard Term 73 ......................................................................................................... 101 Belgard Term 74 ......................................................................................................... 105 Belgard Term 78 ......................................................................................................... 108 Belgard Term 81 ......................................................................................................... 114 Belgard Term 85 ......................................................................................................... 123 Belgard Term 88 ......................................................................................................... 126 The "fast page offset" terms Belgard Term 24 ........................................................................................................... 34 Belgard Term 30 ........................................................................................................... 39

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TABLE OF REFERENCES TO JOINT CLAIM CONSTRUCTION CHART

Joint Claim Construction Chart Tab A, Page Number Belgard Term 33a ......................................................................................................... 40 Belgard Term 33b ......................................................................................................... 48 Belgard Term 38 ........................................................................................................... 50 Belgard Term 40 ........................................................................................................... 54 Belgard Term 48 ........................................................................................................... 66 Belgard Term 57 ........................................................................................................... 74 Belgard Term 69 ........................................................................................................... 94 Belgard Term 75 ......................................................................................................... 104 Belgard Term 83 ......................................................................................................... 120

D.

THE TRANSMETA POWER MANAGEMENT PATENT

"internal conditions" Power Management Term 5 ............................................................................................ 5 Power Management Term 10........................................................................................... 8 "state" Power Management Term 8 ............................................................................................ 7 "clock frequency generator" Power Management Term 3 ............................................................................................ 3 "processor determining" Power Management Term 7 ............................................................................................ 6 Power Management Term 11........................................................................................... 8 "determining . . . maximum[s and a] . . . minimum" Power Management Term 1 ............................................................................................ 1 "determining a frequency and a voltage" Power Management Term 2 ............................................................................................ 2 Power Management Term 6 ............................................................................................ 5 "means for detecting . . . and causing" Power Management Term 4 ............................................................................................ 3

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TABLE OF REFERENCES TO JOINT CLAIM CONSTRUCTION CHART E. THE INTEL POWER MANAGEMENT PATENT Joint Claim Construction Chart Tab B, Page Number

The "supplies to" and "provides to" terms Intel Power Management Term 2 .................................................................................... 1 Intel Power Management Term 4 .................................................................................... 2 "electronic device" Intel Power Management Term 1 .................................................................................... 1 "event" Intel Power Management Term 6 .................................................................................... 2 "thermal band" Intel Power Management Term 8 .................................................................................... 3

F.

THE INTEL ADDRESS TRANSLATION FAMILY

"linear address" Intel Address Translation Term 1 .................................................................................. 10 "physical address" Intel Address Translation Term 4 .................................................................................. 11 The "paging" terms Intel Address Translation Term 5 .................................................................................. 12 The "page frame" and "page frame size" terms Intel Address Translation Term 6 .................................................................................. 12 Intel Address Translation Term 7 .................................................................................. 13 "page size" Intel Address Translation Term 8 .................................................................................. 18 The "control unit" and "paging unit" terms Intel Address Translation Term 2 .................................................................................. 11 Intel Address Translation Term 3 .................................................................................. 11

G.

THE INTEL MULTIMEDIA PROCESSING PATENTS

"packed data" Intel Multmedia Term 1 ................................................................................................ 18

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TABLE OF REFERENCES TO JOINT CLAIM CONSTRUCTION CHART Joint Claim Construction Chart Tab B, Page Number "copying" and "decoding" Intel Multimedia Term 2 ............................................................................................... 19 Intel Multimedia Term 4 ............................................................................................... 20 ". . . two, four, or eight data elements" Intel Multimedia Term 5 ............................................................................................... 20 The "intermediate" terms Intel Multimedia Term 6 [term 2 in JCC for the `634 patent]......................................... 29 Intel Multimedia Term 7 [term 3 in the JCC for the `634 patent] ................................... 29 Intel Multimedia Term 8 [term 4 in the JCC for the `634 patent] ................................... 31

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INTRODUCTION Defendant and counterclaim plaintiff Intel Corporation submits this Opening Claim Construction Brief pursuant to this Court's May 2, 2007 Scheduling Order. Transmeta has asserted 172 claims from eleven patents in this litigation. These patents are from four families, as summarized in the table below. All of the patents in each family claim the same priority date and share a common specification.1 Asserted Transmeta Family Seiko Epson Register Renaming Family Seiko Epson Multi-Type Register Family Belgard Address Translation Family Power Management Family Patents '624 (JA-A at 077-97) '526 (JA-A at 098-119) '433 (JA-A at 120-41) '687 (JA-A at 014-33) '986 (JA-A at 034-55) '449 (JA-A at 056-76) '503 (JA-A at 142-57) '733 (JA-A at 158-74) '668 (JA-A at 175-88) '699 (JA-A at 189-201) '061 (JA-A at 001-13) Asserted Claims 1-4, 6-10, 12-16, 19 1-7, 13-16, 19-20, 26-29, 34 1-4, 6-10, 12-16, 19 1 1, 11 1, 5, 7-10 21-23 1-4, 17-18, 28-30, 36, 39-42, 48-74 1-5, 15-17, 20-22 1-3, 7-10, 13-15 1-8,2 15-54, 56-57

The parties dispute the meaning of 115 terms in these 172 claims. The parties' respective proposed constructions and intrinsic evidence for these terms are set out in Exhibit A to the parties' Joint Claim Construction Statement (D.I. 92). For the Court's convenience, the disputed terms and respective constructions for the four asserted Transmeta patent families are set forth in Intel Appendices A through D to this brief, which can be found in the Joint Appendix at JA-C 130-34 [Intel Appendix A], JA-C 135-40 [Intel Appendix B], JA-C 141-56 [Intel Appendix C],

1

The '061 Transmeta Power Management patent is the only patent of the eleven that Transmeta originally filed itself. The other ten were purchased from others ­ six from Seiko Epson, which in turn purchased the rights to these patents from S-MOS Systems, and four from individual Richard Belgard. Transmeta does not contend that any of its Intel-compatible processors ever practiced any of the claims of the patents purchased from Seiko Epson or Mr. Belgard.
2

Transmeta added claims 6 and 8 of the '061 patent after the parties had already exchanged claim terms to be construed.

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and JA-C 157-59 [Intel Appendix D]. Intel addresses the construction of the disputed terms in the asserted Transmeta patents in Section I, infra. In its counterclaims, Intel asserted seven patents against Transmeta. These Intel patents, and asserted claims, can be grouped into three families, as summarized in the table below: Asserted Intel Family Power Management Patent Address Translation Patents Multimedia Processing Patents Patents '375 (JA-D at 001-10) '554 (JA-D at 011-34) '605 (JA-D at 035-57) '101 (JA-D at 058-86) '275 (JA-D at 087-114) '634 (JA-D at 115-35) '529 (JA-D at 136-58) Asserted Claims 1-4, 6-7, 16-23, 30-31, 33 1-5, 19-21 1-3, 11-12 1-7, 9-15 1-10 3-6, 10, 12, 14 30-31, 33-34, 36-38, 48-50

The 21 disputed terms and respective constructions for the three asserted Intel patent families are set forth in Intel Appendices E through G to this brief, which can be found in the Joint Appendix at JA-F 001 [Intel Appendix E], JA-F 002-03 [Intel Appendix F], and JA-C 004 [Intel Appendix G], and Intel addresses the construction of these terms in Section II, infra. Intel is mindful of the large number of disputed claim terms that the parties are bringing to the Court, and the unusual length of this brief. But the stakes are substantial, and the differences in the approaches taken by the parties are stark. Transmeta would have this Court adopt constructions that would stretch the scope of the Transmeta Patents-in-Suit to cover subject matter well beyond what the applicants represented to have invented to the Patent Office. As described below, the Transmeta Patents-in-Suit have gone through lengthy prosecutions where numerous disclaimers were made and many prior art references distinguished, and the specifications and prosecution histories describe particular characteristics of "the present invention." Transmeta's constructions, almost uniformly, ignore these unambiguous statements and their legal import, and seek to distort their claims like the proverbial "nose of wax" that can be twisted and turned in any direction, in an attempt to cover

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Intel's accused processors, or, as they have done for 70 of the 115 disputed terms in the Transmeta Patents-in-Suit, propose that the jury be given no guidance at all, and that no construction whatsoever be adopted. Transmeta's claims should not be interpreted to cover (or be allowed to cover through no interpretation) what Transmeta (or those they purchased the patents from) did not invent, disclaimed, or distinguished in order to have the claims issued. LEGAL FRAMEWORK A. General Principles of Claim Construction Claim construction is a matter of law. Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448, 1454-56 (Fed. Cir. 1998) (en banc). "[T]he claims of a patent define the invention," but "must be read in view of the specification, of which they are a part." Phillips v. AWH Corp., 415 F.3d 1303, 1312-15 (Fed. Cir. 2005) (en banc). 1. The Specification Is The "Single Best Guide" To Claim Construction

The Federal Circuit rendered the Phillips decision en banc to resolve the conflict arising from two competing methodologies of claim construction: one heavily premised on the "ordinary meaning" of claim terms as evidenced by "objective resources" such as dictionary definitions; the other giving primary weight to the intrinsic record, wherein claim terms are not to be construed "in the abstract, out of [their] particular context." Phillips, 415 F.3d at 1319-24. The Federal Circuit's focus on determining a construction true to the invention led the court to reject the dictionary-centric methodology in favor of the contextual methodology. Id. As a result, it is "entirely appropriate for a court, when conducting claim construction, to rely heavily on the written description for guidance as to the meaning of the claims," because the specification "[u]sually is dispositive; it is the single best guide to the meaning of a disputed term." Id. at 1315-17. The proper construction "can only be determined and confirmed with a full understanding of what the inventors actually invented and intended to envelop with the

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claim. The construction that stays true to the claim language and most naturally aligns with the patent's description of the invention will be, in the end, the correct construction." Id. at 1316. The claims of a patent cannot be construed more broadly than "the invention that is set forth in the specification." On Demand Machine Corp. v. Ingram Indus., Inc., 442 F.3d 1331, 1340 (Fed. Cir. 2006). While it is inappropriate to limit the claims to "an example of how to practice the invention" described in the specification, it is appropriate to rely on "the manner in which the patentee uses a term within the specification" to determine whether the patentee "intends for the claims and the embodiments in the specification to be strictly coextensive." Phillips, 415 F.3d at 1323. In addition, the claims may be limited to an embodiment described in the specification where there is "nothing in the context to indicate that the patentee contemplated any alternative." Id. (citation omitted). In fact, "the specification may reveal an intentional disclaimer, or disavowal, of claim scope by the inventor." Id. at 1316. "Where the specification makes clear that the invention does not include a particular feature, that feature is deemed to be outside the reach of the claims of the patent, even though the language of the claims, read without reference to the specification, might be considered broad enough to encompass the feature in question." SciMed Life Sys. v. Advanced Cardiovascular Sys., 242 F.3d 1337, 1341 (Fed. Cir. 2001). For instance, "repeated derogatory statements" concerning a particular aspect of the art "are the equivalent of disavowal of that subject matter from the scope of the patent's claims." Honeywell Int'l, Inc. v. ITT Indus., 452 F.3d 1312, 1320 (Fed. Cir. 2006). 2. Statements Made During Prosecution May Also Limit The Claims

It is also appropriate for a court conducting claim construction to rely on the inventor's statements to the Patent Office during prosecution, which "demonstrat[e] how the inventor understood the invention and whether the inventor limited the invention in the course of prosecution, making the claim scope narrower than it would otherwise be." Phillips, 415 F.3d at 4

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1317; see also Ormco Corp. v. Align Tech., Inc., 498 F.3d 1307, 1316 (Fed. Cir. 2007) ("[T]o attribute to the claims a meaning broader than any indicated in the patents and their prosecution history would be to ignore the totality of the facts of the case and exalt slogans over real meaning."); Std. Oil Co. v. Am. Cyanamid Co., 774 F.2d 448, 452 (Fed. Cir. 1985) ("[T]he prosecution history [ ] limits the interpretation of claims so as to exclude any interpretation that may have been disclaimed or disavowed during prosecution [ ] to obtain claim allowance."). 3. Extrinsic Evidence Is Generally "Less Reliable"

While extrinsic evidence, including dictionaries, may be useful, the Federal Circuit views "extrinsic evidence in general as less reliable." Phillips, 415 F.3d at 1318. As a result, extrinsic evidence should only be considered "in the context of the intrinsic evidence," i.e., the claims, specification, and prosecution history. Id. at 1319; see also Old Town Canoe Co. v. Confluence Holdings Corp., 448 F.3d 1309, 1318 (Fed. Cir. 2006) (patentee "is not entitled to a claim construction divorced from the context of the written description and prosecution history"). B. Construction of Means-Plus-Function Terms Use of the word "means" creates a presumption that § 112, ¶ 6 applies. See Personalized Media Comm., LLC v. Int'l Trade Comm'n, 161 F.3d 696, 703-04 (Fed. Cir. 1998). The claim must recite "sufficient structure" to "perform entirely the recited function" to overcome this presumption. Sage Prods. v. Devon Indus., Inc., 126 F.3d 1420, 1427-28 (Fed. Cir. 1997). Construction of a means-plus-function term is a two-part process: (1) determining the claimed function and (2) identifying the structure corresponding to that function. See JVW Enter., Inc. v. Interact Accessories, Inc., 424 F.3d 1324, 1330 (Fed. Cir. 2005). A structure only qualifies as corresponding structure "if the specification or prosecution history clearly links or associates that structure to the function recited in the claim." Default Proof Credit Card Sys., Inc. v. Home Depot U.S.A., Inc., 412 F.3d 1291, 1297-98 (Fed. Cir. 2005). 5

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ARGUMENT I. A. THE TRANSMETA PATENTS-IN-SUIT

THE SEIKO EPSON REGISTER RENAMING PATENTS 1. Introduction To The Register Renaming Patents

The Register Renaming patents are based on a "reduced instruction set computer" ("RISC") processor project at a company called S-MOS Systems in the early 1990s that was never commercialized. After S-MOS filed the applications which later issued as the Seiko Epson Register Renaming patents, as well as the applications that later issued as the Multi-Type Register patents discussed below, S-MOS sold its rights in these patents and the related technology to Seiko Epson, which also never commercialized the technology. Seiko Epson sold its rights in the Register Renaming patents (and the Multi-Type Register patents) to Transmeta in 2001. Transmeta appears to have purchased the Seiko Epson patents for the sole purpose of asserting those patents against others, for Transmeta concedes that it has never practiced any of the inventions of the asserted Seiko Epson claims. The Register Renaming patents Transmeta acquired are directed to a very specific technique for register renaming. Register renaming allows a processor to perform instructions out of program order, which can improve computer efficiency. As demonstrated below, Transmeta would have this Court adopt constructions that would distort the Register Renaming patents to cover prior art register renaming techniques that were disclaimed in the specification and distinguished during prosecution. This is improper. In particular, the Register Renaming applicants conceded to the Patent Office that it was well known in the art to use a structure that the applicants referred to as a "temporary buffer" to perform register renaming. In order to distinguish their claimed register renaming invention using a temporary buffer from prior art temporary buffers, the applicants represented that their

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claims were directed to a specific register renaming technique where the position of each instruction in a so-called "instruction window" maps one-for-one to each storage location in the temporary buffer. The applicants also explicitly contrasted their invention from what they described in the specification as "conventional register renaming." Transmeta's attempt to distort the Register Renaming patents to cover the very prior art register renaming techniques distinguished during prosecution is improper and should be rejected. (a) The Problem Addressed By The Register Renaming Patents

The Register Renaming patents address the problem of resolving certain "dependencies" that arise when computer program instructions are performed out of order. '624 at 1:44-49. The specification explains that there are two categories of dependencies: "true" dependencies and "storage conflict" dependencies. Id. at 1:52-64. True dependencies occur when an instruction uses the result of a prior instruction as an input (id. at 8:22-24), and therefore the later instruction cannot begin until the earlier instruction has been performed. Id. at 1:59-62; 8:30-31. Storage conflict dependencies occur when the outputs of two different instructions are to be stored in the same place (an "output" dependency), or the output of an instruction is to be stored in the same place as the input of a prior instruction (an "anti-dependency"). Id. at 8:24-28. In contrast to true dependencies which cannot be eliminated, storage conflict dependencies can be eliminated by creating additional storage locations. Id. at 2:11-18. The specification acknowledges that it was well known in the art to use a temporary buffer (or "reorder buffer") to create the additional storage locations required to resolve storage conflict dependencies. Id. at 2:20-25; 4:24-47; 6:4-15. In prior art temporary buffers, each instruction is assigned a location in the temporary buffer in program order. Id. at 4:24-47; JA-A at 998-1003 [Johnson, "Superscalar Microprocessor Design" ("Johnson"), pp. 48-50, 92-94]. The processor may then execute the instructions out of program order without worrying about 7

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storage conflict dependencies. '624 at 4:24-47. After an instruction is performed, its result is written into the temporary buffer location assigned to that instruction. Id. The problem addressed by the Register Renaming patents is finding where in the temporary buffer the result of a particular instruction is stored. During prosecution, the applicants criticized the prior art approaches of using a complex associative look-up or a mapping table as expensive and time consuming. See, e.g., '624 at 6:51-54; JA-A at 459 ['499 FH at 9/30/94 Response, p. 10]; id. at 552-54 ['433 FH at 12/27/00 Reply, pp. 4-6]. (b) The Invention Claimed In The Register Renaming Patents

The specific technique that the Register Renaming patents propose to address the prior art disadvantages is mapping each instruction to a specific, predetermined location in the temporary buffer based on the instruction's position in what the patents refer to as an "instruction window": In accordance with the present invention, instructions are processed in buckets. Each bucket comprises a predetermined number of instructions. The temporary buffer is set equal to the predetermined size of the buckets. Thus, each instruction's outputs (execution results) are stored in a specific, predetermined location in the temporary buffer. That predetermined location is unique to one instruction while the corresponding bucket is being processed. Thus, once dependencies between instructions are determined, the location within the temporary buffer of inputs required for a next instruction are known a priori. JA-A at 440 ['499 FH at 10/14/93 Response, p. 5] (emphasis added unless otherwise noted); id. at 460 [id. at 9/30/94 Response, p. 11] ("the location at which an instruction's results are stored in a temporary buffer is related to the location of that instruction in the instruction window"). As a result, the processor is able to find instruction results in the temporary buffer without a complex associative look-up or mapping table because each location in the "instruction window" maps to a specific, predetermined location in the temporary buffer. Transmeta's constructions are improper because they ignore what the applicants told the Patent Office was the heart of their invention and seek to capture the very prior art distinguished to obtain the patents.

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2.

The "instruction window" terms (Renaming Terms 3 and 11)

Each of the asserted claims requires an "instruction window" ('624 and '433) or an "instruction buffer" ('526). The table below shows the parties' respective constructions for "instruction window." The parties agree that "instruction buffer" refers to the physical location where the instructions in the instruction window are stored. Term "instruction window" [Renaming Term 3]3 Intel's Construction the group of instructions for which the computer system determines dependencies at the same time, wherein the number of instructions in the instruction window is equal in size to the number of storage locations in the temporary buffer4 Transmeta's Construction a group of the instructions resulting from decoding that have not been retired

There are two disputes between the parties. First, the parties dispute whether the group of instructions in the window are the instructions that are compared against each other for true dependencies (Intel's position) or the instructions that have been decoded but not yet retired (Transmeta's position). Second, the parties dispute whether the instruction window is the same size as the temporary buffer (Intel's position) or can be any size (Transmeta's position). (a) The Specification Consistently And Repeatedly Describes The Instruction Window As The Group Of Instructions Compared Against Each Other For True Dependencies

As explained above, using a temporary buffer only resolves storage conflict dependencies. When there is a true dependency between two instructions, the later instruction cannot be performed until after the earlier instruction from which it depends is performed. '624

3

For the page in the Joint Claim Construction Chart where the construction for each term could be found, please see the Table of References to the Joint Claim Construction Chart at page viii.
4

Intel's construction is a slight modification of the construction Intel proposed in the Joint Claim Chart to make clear that it is the number of instructions in the instruction window that is equal in size to the number of storage locations in the temporary buffer.

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at 8:30-31. The claimed invention uses a "data dependency checker" ("DDC") to "locate the [true] dependencies between the instructions for a group of instructions." Id. at 6:36-37. The specification consistently and repeatedly describes this "group of instructions" for which true dependencies are determined as the instructions in the "instruction window." See, e.g., 3:2-4 ("the number of dependencies between a group of instructions, such as a group of instructions in a window"); 9:43-45 ("All source registers are compared with all previous destination registers for each instruction in window 102."). The instructions in the instruction window are "defined" as "current instructions" (id. at 8:42-44), which are also described as the group of instructions for which the computer system determines dependencies at the same time. See, e.g., id. at 8:31-38 (renaming circuitry is "used to locate the input dependencies between current instructions"); 9:37-45 ("DDC 108 determines where the input dependencies are between the current instructions" by comparing "[a]ll source registers" with "all previous destination registers for each instruction in window 102"). The "instruction window" therefore is the group of instructions for which the computer system determines true dependencies at the same time. (b) The Instruction Window Must Be The Same Size As The Temporary Buffer For The One-To-One Mapping Scheme To Work

As explained above, the applicants distinguished the claimed invention from prior art temporary buffers based on how instructions are mapped to temporary buffer locations. In order for each instruction to map to a specific, predetermined location in the temporary buffer based on that instruction's position in the "instruction window," each position in the instruction window must map one-to-one with each location in the temporary buffer. During prosecution, the applicants explained that their one-to-one mapping scheme worked by setting the number of instructions in the instruction window ­ which includes a predetermined number of "buckets" ('624 at 7:63-8:10) ­ "equal" to the number of storage locations in the temporary buffer:

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In accordance with the present invention, instructions are processed in buckets. Each bucket comprises a predetermined number of instructions. The temporary buffer is set equal to the predetermined size of the buckets. JA-A at 440 ['499 FH at 10/14/93 Response, p. 5]. See Gaus v. Conair Corp., 363 F.3d 1284, 1290 (Fed. Cir. 2004) ("according to the invention" language describes "the invention itself"). As a result, the number of instructions in the instruction window must be equal in size to the number of storage locations in the temporary buffer. This interpretation is consistent with the only embodiment described in the specification, in which the instruction window includes eight instructions and the temporary buffer has eight storage locations. See, e.g., '624 at 8:2-4 ("window 102 comprises eight instructions"); id. at 8:50-52 ("group of 8 temporary buffers"). (c) Transmeta's Construction Is Inconsistent With The Preferred Embodiment

In addition to not including the requirements set forth above, Transmeta's construction is inconsistent with the preferred embodiment. See Chimie v. PPG Indus., Inc., 402 F.3d 1371, 1377 (Fed. Cir. 2005) ("As we have frequently stated, a construction that would not read on the preferred embodiment would rarely, if ever be correct.") (quotations omitted). In the preferred embodiment, the instruction window includes two buckets of four instructions each. '624 at 7:63-8:4. The specification explains that the four instructions in each bucket remain part of the "instruction window" until all four are retired.5 Id. at 8:6-10. Instructions are retired in program order; that is, the first instruction retires first, the second instruction retires second, etc. Id. at 8:63-9:7. This is inconsistent with Transmeta's construction, which defines the "instruction window" as the decoded instructions "that have not

5

The specification explains that an instruction is "retired" when its result is moved from the temporary buffer to the register file. '624 at 8:56-62.

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been retired," because the first three instructions in the bucket will remain part of the instruction window ­ even after they retire ­ until the fourth instruction in the bucket also retires. Id. 3. The "determined by" and "assigned to" terms (Renaming Terms 4, 10, 12, 15, 17, and 18)

Each of the asserted claims requires each instruction to be mapped to a location in the temporary buffer. The "determined by" and "assigned to" terms listed above specify how the instructions are mapped to temporary buffer locations. The table below shows the parties' respective constructions for these term in claim 1 of the '624 and '433 patents. Term "one of a plurality of storage locations being determined by a location of said instruction in an instruction window" [Renaming Term 4] "said one of said plurality of storage locations being assigned to said instruction in said instruction window" [Renaming Term 17] Intel's Construction each instruction in the instruction window maps to a specific, predetermined location in the temporary buffer based on that instruction's position in the instruction window each instruction in the instruction window maps to a specific, predetermined location in the temporary buffer based on that instruction's position in the instruction window Transmeta's Construction storage locations are assigned based on the program order of instructions in the instruction window

No construction ­ plain and ordinary meaning If the Court decides a construction is necessary, this term means one of the plurality of storage locations in the temporary buffer is assigned to the instruction in the instruction window

The dispute between the parties is whether each instruction maps to a specific, predetermined location based on its position in the instruction window (Intel's position) or is assigned a location based on its program order (Transmeta's position for the '624 patent) or in any order (Transmeta's position for the '526 and '433 patents). As explained above, the applicants distinguished the claimed invention from prior art temporary buffers based on how instructions are mapped to temporary buffer locations. In the specification, the applicant clearly described the "present invention" as "automatically map[ping]

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each instruction [to] a predetermined temporary buffer location." '624 at 6:49-52; see also id. at 8:52-56 ("When an instruction completes . . . its result is stored in its preassigned location."). Likewise, during prosecution, the applicants distinguished the claimed invention from the prior art as allowing the processor to find the result of a particular instruction in the temporary buffer without a complex associative look-up or mapping table because each instruction automatically maps to a "specific, predetermined location in the temporary buffer": In accordance with the present invention, instructions are processed in buckets. Each bucket comprises a predetermined number of instructions. The temporary buffer is set equal to the predetermined size of the buckets. Thus, each instruction's outputs (execution results) are stored in a specific, predetermined location in the temporary buffer. That predetermined location is unique to one instruction while the corresponding bucket is being processed. Thus, once dependencies between instructions are determined, the location within the temporary buffer of inputs required for a next instruction are known a priori. JA-A at 440 ['499 FH at 10/14/93 Response, p. 5]. The applicants explained that the specific, predetermined location in the temporary buffer for each instruction is based on that instruction's position in the instruction window: According to Applicants' specification, each instruction always writes to the same place in the temporary buffer. That is, the location at which an instruction's results are stored in a temporary buffer is related to the location of that instruction in the instruction window. Id. at 460 ['499 FH at 9/30/94 Response, p. 11]. Because the applicants distinguished their invention from prior art temporary buffers ­ which assigned locations in the temporary buffer in program order (see, e.g., JA-A at 998-1003 [Johnson, pp. 48-50, 92-94]) ­ based on how the instructions are mapped to temporary buffer locations, each instruction must map to a specific, predetermined location in the temporary buffer based on the instruction's position in the instruction window. See Ormco, 498 F.3d at 1316 ("[T]o attribute to the claims a meaning broader than any indicated in the patents and their prosecution history would be to ignore the totality of the facts of the case and exalt slogans over 13

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real meaning."). This interpretation is consistent with the only embodiment described, in which, for example, slot 0 in the instruction window always maps to location 0 in the temporary buffer. See, e.g., '624 at 13:58 ("t0=inst. 0's slot in temporary buffer"). 4. The "computer system" terms (Renaming Terms 2 and 14; Multi-Type Terms 1 and 17)

Most of the asserted claims of the Register Renaming patents are directed to a "computer system" or "processor." The table below shows the parties' respective constructions for these terms. The related terms in the Multi-Type Register patents, i.e., "processor" and "central processing unit," which appear in all of the Multi-Type Register asserted claims, involve the same dispute and are therefore discussed in this section as well.6 Term "computer system" [Renaming Term 2] "processor" [Renaming Term 14 and Multi-Type Term 17] Intel's Construction a reduced instruction set computer a processor in a reduced instruction set computer Transmeta's Construction No construction necessary ­ plain and ordinary meaning No construction necessary ­ plain and ordinary meaning

The dispute between the parties is whether the claims are limited to resolving storage conflict dependencies in a reduced instruction set computer ("RISC") (Intel's position) or also cover doing so in a complex instruction set computer ("CISC") (Transmeta's position). For the Register Renaming patents, it is clear from the entirety of the specification that "[t]he present invention" is directed to RISC computers. The first sentence of the register renaming specification states that "the present invention" relates to "reduced instruction set computers (RISC)." '624 at 1:29-33. The first sentence of the "Summary of the Invention" section of the register renaming specification also describes "[t]he present invention [as] directed

6

The Register Renaming and Multi-Type Register patents include overlapping named inventors and are based on the same RISC processor project discussed above.

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to instruction scheduling including register renaming and instruction issuing for superscalar RISC computers." Id. at 6:19-21; see Verizon Servs. Corp. v. Vonage Holdings Corp., -- F.3d. --, C.A. Nos. 2007-1240, -1274, 2007 U.S. App. LEXIS 22737, at *31-32 (Fed. Cir. Sept. 26, 2007) ("When a patent thus describes the features of the `present invention' as a whole, this description limits the scope of the invention."); Watts v. XL Sys., Inc., 232 F.3d 877, 882-83 (Fed. Cir. 2000) ("[T]he specification actually limits the invention" by "stating that `[t]he present invention utilizes [the varying taper angle] feature.'"). The abstract for all three Register Renaming patents also describes the invention as a "register renaming system for out-of-order execution of a set of reduced instruction set computer instructions." See, e.g., '624 at Abstract. Even the titles for all three Register Renaming patents ­ and all three Multi-Type Register patents ­ include the term "RISC." See Honeywell, 452 F.3d at 1318 ("the public is entitled to take the patentee at his word" when he repeatedly stated that "this invention" or "present invention" was a fuel filter). Similarly, in the Multi-Type Register patents, the applicants explicitly distinguished the claimed RISC invention from CISC processors: [T]he invention may be characterized as a RISC microprocessor having a register file optimally configured for use in the execution of RISC instructions, as opposed to conventional register files which are sufficient for use in the execution of CISC (complex instruction set computing) instructions by CISC processors. '687 at 5:50-55. In so doing, the applicants disclaimed CISC processors. See SciMed, 242 F.3d at 1341 ("Where the specification makes